Multiplexed Signals
Table 1. PORT Function Multiplexing, 14 and 20 Pins
VQFN 20-Pin |
SOIC 20-Pin |
SOIC 14-Pin |
Pin Name(1,2) |
Other/Special |
ADC0 |
AC0 |
USART0 |
SPI0 |
TWI0 |
TCA0 |
TCB0 |
CCL |
19 |
16 |
10 |
PA0 |
RESET/UPDI |
AIN0 |
|
|
|
|
|
|
LUT0-IN0 |
20 |
17 |
11 |
PA1 |
|
AIN1 |
|
TxD(3) |
MOSI |
|
|
|
LUT0-IN1 |
1 |
18 |
12 |
PA2 |
EVOUT0 |
AIN2 |
|
RxD(3) |
MISO |
|
|
|
LUT0-IN2 |
2 |
19 |
13 |
PA3 |
EXTCLK |
AIN3 |
|
XCK(3) |
SCK |
|
WO3 |
|
|
3 |
20 |
14 |
GND |
|
|
|
|
|
|
|
|
|
4 |
1 |
1 |
VDD |
|
|
|
|
|
|
|
|
|
5 |
2 |
2 |
PA4 |
|
AIN4 |
|
XDIR(3) |
SS |
|
WO4 |
|
LUT0-OUT |
6 |
3 |
3 |
PA5 |
|
AIN5 |
OUT |
|
|
|
WO5 |
WO |
|
7 |
4 |
4 |
PA6 |
|
AIN6 |
AINN0 |
|
MOSI(3)(4) |
|
|
|
|
8 |
5 |
5 |
PA7 |
|
AIN7 |
AINP0 |
|
MISO(3)(4) |
|
|
|
LUT1-OUT |
9 |
6 |
|
PB5 |
CLKOUT |
AIN8 |
AINP1 |
|
|
|
WO2(3) |
|
|
10 |
7 |
|
PB4 |
|
AIN9 |
AINN1 |
|
|
|
WO1(3) |
|
LUT0-OUT(3) |
11 |
8 |
6 |
PB3 |
|
|
|
RxD |
|
|
WO0(3) |
|
|
12 |
9 |
7 |
PB2 |
EVOUT1 |
|
|
TxD |
|
|
WO2 |
|
|
13 |
10 |
8 |
PB1 |
|
AIN10 |
|
XCK |
|
SDA |
WO1 |
|
|
14 |
11 |
9 |
PB0 |
|
AIN11 |
|
XDIR |
|
SCL |
WO0 |
|
|
15 |
12 |
|
PC0 |
|
|
|
|
SCK(3) |
|
|
WO(3) |
|
16 |
13 |
|
PC1 |
|
|
|
|
MISO(3)(4) |
|
|
|
LUT1-OUT(3) |
17 |
14 |
|
PC2 |
EVOUT2 |
|
|
|
MOSI(3)(4) |
|
|
|
|
18 |
15 |
|
PC3 |
|
|
|
|
SS(3) |
|
WO3(3) |
|
LUT1-IN0 |
Notes:
- 1.Pin names are of type Pxn, with x being the PORT instance (A, B) and n the pin number. The notation for signals is PORTx_PINn. All pins can be used as event input.
- 2.All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full asynchronous detection.
- 3. Alternate pin positions. For selecting the alternate positions, refer to section PORTMUX - Port Multiplexer.
- 4.Alternate pins for SPI MISO and MOSI are respectively at PA7 and PA6 for 14-pin devices and PC1 and PC2 for 20-pin devices.
Table 2. PORT Function Multiplexing, Eight PinsSOIC 8-Pin |
Pin Name(1,2) |
Other/Special |
ADC0 |
AC0 |
USART0 |
SPI0 |
TWI0 |
TCA0 |
TCB0 |
CCL |
6 |
PA0 |
RESET/UPDI |
AIN0 |
|
XDIR |
SS |
|
|
|
LUT0-IN0 |
4 |
PA1 |
|
AIN1 |
|
TxD(3) |
MOSI |
SDA |
WO1 |
|
LUT0-IN1 |
5 |
PA2 |
EVOUT0 |
AIN2 |
|
RxD(3) |
MISO |
SCL |
WO2 |
|
LUT0-IN2 |
7 |
PA3 |
EXTCLK |
AIN3 |
OUT |
XCK |
SCK |
|
WO0/WO3 |
|
|
8 |
GND |
|
|
|
|
|
|
|
|
|
1 |
VDD |
|
|
|
|
|
|
|
|
|
2 |
PA6 |
|
AIN6 |
AINN0 |
TxD |
MOSI(3) |
|
|
WO0 |
LUT0-OUT |
3 |
PA7 |
|
AIN7 |
AINP0 |
RxD |
MISO(3) |
|
WO0(3) |
|
LUT1-OUT |
Notes:
- 1.Pin names are of type Pxn, with x being the PORT instance (A, B) and n the pin number. Notation for signals is PORTx_PINn. All pins can be used as event inputs.
- 2.All pins can be used for external interrupts, where pins Px2 and Px6 of each port have full asynchronous detection.
- 3. Alternate pin positions. For selecting the alternate positions, refer to section PORTMUX - Port Multiplexer.