Contents

Introduction Features 3. Silicon Errata and Data Sheet Clarification Document 4. tinyAVR 0-series Overview 4.1. Configuration Summary 4.1.1. Peripheral Summary 5. Block Diagram 6. Pinout 6.1. 8-Pin SOIC 6.2. 14-Pin SOIC 6.3. 20-Pin SOIC 6.4. 20-Pin VQFN 7. I/O Multiplexing and Considerations 7.1. Multiplexed Signals 8. Memories 8.1. Overview 8.2. Memory Map 8.3. In-System Reprogrammable Flash Program Memory 8.4. SRAM Data Memory 8.5. EEPROM Data Memory 8.6. User Row 8.7. Signature Bytes 8.8. I/O Memory 8.8.1. Register Summary 8.8.2. Register Description 8.8.2.1. General Purpose I/O Register n 8.9. Memory Section Access from CPU and UPDI on Locked Device 8.10. Configuration and User Fuses (FUSE) 8.10.1. Signature Row Summary 8.10.2. Signature Row Description 8.10.2.1. Device ID n 8.10.2.2. Serial Number Byte n 8.10.2.3. Temperature Sensor Calibration n 8.10.2.4. OSC16 Error at 3V 8.10.2.5. OSC16 Error at 5V 8.10.2.6. OSC20 Error at 3V 8.10.2.7. OSC20 Error at 5V 8.10.3. Fuse Summary - FUSE 8.10.4. Fuse Description 8.10.4.1. Watchdog Configuration 8.10.4.2. BOD Configuration 8.10.4.3. Oscillator Configuration 8.10.4.4. System Configuration 0 8.10.4.5. System Configuration 1 8.10.4.6. Application Code End 8.10.4.7. Boot End 8.10.4.8. Lockbits 9. Peripherals and Architecture 9.1. Peripheral Address Map 9.2. Interrupt Vector Mapping 9.3. System Configuration (SYSCFG) 9.3.1. Register Summary 9.3.2. Register Description 9.3.2.1. Device Revision ID Register 10. AVR CPU 10.1. Features 10.2. Overview 10.3. Architecture 10.4. Arithmetic Logic Unit (ALU) 10.4.1. Hardware Multiplier 10.5. Functional Description 10.5.1. Program Flow 10.5.2. Instruction Execution Timing 10.5.3. Status Register 10.5.4. Stack and Stack Pointer 10.5.5. Register File 10.5.5.1. The X-, Y-, and Z-Registers 10.5.6. Accessing 16-bit Registers 10.5.7. Configuration Change Protection (CCP) 10.5.7.1. Sequence for Write Operation to Configuration Change Protected I/O Registers 10.5.7.2. Sequence for Execution of Self-Programming 10.5.8. On-Chip Debug Capabilities 10.6. Register Summary 10.7. Register Description 10.7.1. CCP 10.7.2. SP 10.7.3. SREG 11. NVMCTRL - Nonvolatile Memory Controller 11.1. Features 11.2. Overview 11.2.1. Block Diagram 11.3. Functional Description 11.3.1. Memory Organization 11.3.1.1. Flash 11.3.1.2. EEPROM 11.3.1.3. User Row 11.3.2. Memory Access 11.3.2.1. Read 11.3.2.2. Page Buffer Load 11.3.2.3. Programming 11.3.2.4. Commands 11.3.2.4.1. Write Page Command 11.3.2.4.2. Erase Page Command 11.3.2.4.3. Erase/Write Page Command 11.3.2.4.4. Page Buffer Clear Command 11.3.2.4.5. Chip Erase Command 11.3.2.4.6. EEPROM Erase Command 11.3.2.4.7. Write Fuse Command 11.3.2.5. Write Access after Reset 11.3.3. Preventing Flash/EEPROM Corruption 11.3.4. Interrupts 11.3.5. Sleep Mode Operation 11.3.6. Configuration Change Protection 11.4. Register Summary 11.5. Register Description 11.5.1. Control A 11.5.2. Control B 11.5.3. Status 11.5.4. Interrupt Control 11.5.5. Interrupt Flags 11.5.6. Data 11.5.7. Address 12. CLKCTRL - Clock Controller 12.1. Features 12.2. Overview 12.2.1. Block Diagram - CLKCTRL 12.2.2. Signal Description 12.3. Functional Description 12.3.1. Sleep Mode Operation 12.3.2. Main Clock Selection and Prescaler 12.3.3. Main Clock After Reset 12.3.4. Clock Sources 12.3.4.1. Internal Oscillators 12.3.4.1.1. 16/20 MHz Oscillator (OSC20M) 12.3.4.1.1.1. OSC20M Stored Frequency Error Compensation 12.3.4.1.2. 32.768 kHz Oscillator (OSCULP32K) 12.3.4.2. External Clock Sources 12.3.4.2.1. External Clock (EXTCLK) 12.3.5. Configuration Change Protection 12.4. Register Summary 12.5. Register Description 12.5.1. Main Clock Control A 12.5.2. Main Clock Control B 12.5.3. Main Clock Lock 12.5.4. Main Clock Status 12.5.5. 16/20 MHz Oscillator Control A 12.5.6. 16/20 MHz Oscillator Calibration A 12.5.7. 16/20 MHz Oscillator Calibration B 12.5.8. 32.768 kHz Oscillator Control A 13. SLPCTRL - Sleep Controller 13.1. Features 13.2. Overview 13.2.1. Block Diagram 13.3. Functional Description 13.3.1. Initialization 13.3.2. Operation 13.3.2.1. Sleep Modes 13.3.2.2. Wake-up Time 13.3.3. Debug Operation 13.4. Register Summary 13.5. Register Description 13.5.1. Control A 14. RSTCTRL - Reset Controller 14.1. Features 14.2. Overview 14.2.1. Block Diagram 14.2.2. Signal Description 14.3. Functional Description 14.3.1. Initialization 14.3.2. Operation 14.3.2.1. Reset Sources 14.3.2.1.1. Power-on Reset (POR) 14.3.2.1.2. Brown-out Detector (BOD) Reset 14.3.2.1.3. External Reset 14.3.2.1.4. Watchdog Reset 14.3.2.1.5. Software Reset 14.3.2.1.6. Unified Program and Debug Interface (UPDI) Reset 14.3.2.1.7. Domains Affected By Reset 14.3.2.2. Reset Time 14.3.3. Sleep Mode Operation 14.3.4. Configuration Change Protection 14.4. Register Summary 14.5. Register Description 14.5.1. Reset Flag Register 14.5.2. Software Reset Register 15. CPUINT - CPU Interrupt Controller 15.1. Features 15.2. Overview 15.2.1. Block Diagram 15.3. Functional Description 15.3.1. Initialization 15.3.2. Operation 15.3.2.1. Enabling, Disabling and Resetting 15.3.2.2. Interrupt Vector Locations 15.3.2.3. Interrupt Response Time 15.3.2.4. Interrupt Priority 15.3.2.4.1. Non-Maskable Interrupts 15.3.2.4.2. High-Priority Interrupt 15.3.2.4.3. Normal-Priority Interrupts 15.3.2.4.3.1. Static Scheduling 15.3.2.4.3.2. Modified Static Scheduling 15.3.2.4.3.3. Round Robin Scheduling 15.3.2.5. Compact Vector Table 15.3.3. Debug Operation 15.3.4. Configuration Change Protection 15.4. Register Summary 15.5. Register Description 15.5.1. Control A 15.5.2. Status 15.5.3. Interrupt Priority Level 0 15.5.4. Interrupt Vector with Priority Level 1 16. EVSYS - Event System 16.1. Features 16.2. Overview 16.2.1. Block Diagram 16.2.2. Signal Description 16.2.3. System Dependencies 16.2.3.1. Clocks 16.2.3.2. I/O Lines 16.3. Functional Description 16.3.1. Initialization 16.3.2. Operation 16.3.2.1. Event User Multiplexer Setup 16.3.2.2. Event System Channel 16.3.2.3. Event Generators 16.3.2.4. Software Event 16.3.3. Interrupts 16.3.4. Sleep Mode Operation 16.3.5. Debug Operation 16.3.6. Synchronization 16.3.7. Configuration Change Protection 16.4. Register Summary 16.5. Register Description 16.5.1. Asynchronous Channel Strobe 16.5.2. Synchronous Channel Strobe 16.5.3. Asynchronous Channel n Generator Selection 16.5.4. Synchronous Channel n Generator Selection 16.5.5. Asynchronous User Channel n Input Selection 16.5.6. Synchronous User Channel n Input Selection 17. PORTMUX - Port Multiplexer 17.1. Overview 17.2. Register Summary 17.3. Register Description 17.3.1. Control A 17.3.2. Control B 17.3.3. Control C 17.3.4. Control D 18. PORT - I/O Pin Configuration 18.1. Features 18.2. Overview 18.2.1. Block Diagram 18.2.2. Signal Description 18.3. Functional Description 18.3.1. Initialization 18.3.2. Operation 18.3.2.1. Basic Functions 18.3.2.2. Pin Configuration 18.3.2.3. Virtual Ports 18.3.2.4. Peripheral Override 18.3.3. Interrupts 18.3.3.1. Asynchronous Sensing Pin Properties 18.3.4. Events 18.3.5. Sleep Mode Operation 18.3.6. Debug Operation 18.4. Register Summary - PORTx 18.5. Register Description - PORTx 18.5.1. Data Direction 18.5.2. Data Direction Set 18.5.3. Data Direction Clear 18.5.4. Data Direction Toggle 18.5.5. Output Value 18.5.6. Output Value Set 18.5.7. Output Value Clear 18.5.8. Output Value Toggle 18.5.9. Input Value 18.5.10. Interrupt Flags 18.5.11. Pin n Control 18.6. Register Summary - VPORTx 18.7. Register Description - VPORTx 18.7.1. Data Direction 18.7.2. Output Value 18.7.3. Input Value 18.7.4. Interrupt Flags 19. BOD - Brown-out Detector 19.1. Features 19.2. Overview 19.2.1. Block Diagram 19.3. Functional Description 19.3.1. Initialization 19.3.2. Interrupts 19.3.3. Sleep Mode Operation 19.3.4. Configuration Change Protection 19.4. Register Summary 19.5. Register Description 19.5.1. Control A 19.5.2. Control B 19.5.3. VLM Control A 19.5.4. Interrupt Control 19.5.5. VLM Interrupt Flags 19.5.6. VLM Status 20. VREF - Voltage Reference 20.1. Features 20.2. Overview 20.2.1. Block Diagram 20.3. Functional Description 20.3.1. Initialization 20.4. Register Summary 20.5. Register Description 20.5.1. Control A 20.5.2. Control B 21. WDT - Watchdog Timer 21.1. Features 21.2. Overview 21.2.1. Block Diagram 21.2.2. Signal Description 21.3. Functional Description 21.3.1. Initialization 21.3.2. Clocks 21.3.3. Operation 21.3.3.1. Normal Mode 21.3.3.2. Window Mode 21.3.3.3. Configuration Protection and Lock 21.3.4. Sleep Mode Operation 21.3.5. Debug Operation 21.3.6. Synchronization 21.3.7. Configuration Change Protection 21.4. Register Summary - WDT 21.5. Register Description 21.5.1. Control A 21.5.2. Status 22. TCA - 16-bit Timer/Counter Type A 22.1. Features 22.2. Overview 22.2.1. Block Diagram 22.2.2. Signal Description 22.3. Functional Description 22.3.1. Definitions 22.3.2. Initialization 22.3.3. Operation 22.3.3.1. Normal Operation 22.3.3.2. Double Buffering 22.3.3.3. Changing the Period 22.3.3.4. Compare Channel 22.3.3.4.1. Waveform Generation 22.3.3.4.2. Frequency (FRQ) Waveform Generation 22.3.3.4.3. Single-Slope PWM Generation 22.3.3.4.4. Dual-Slope PWM 22.3.3.4.5. Port Override for Waveform Generation 22.3.3.5. Timer/Counter Commands 22.3.3.6. Split Mode - Two 8-Bit Timer/Counters 22.3.4. Events 22.3.5. Interrupts 22.3.6. Sleep Mode Operation 22.4. Register Summary - Normal Mode 22.5. Register Description - Normal Mode 22.5.1. Control A - Normal Mode 22.5.2. Control B - Normal Mode 22.5.3. Control C - Normal Mode 22.5.4. Control D - Normal Mode 22.5.5. Control Register E Clear - Normal Mode 22.5.6. Control Register E Set - Normal Mode 22.5.7. Control Register F Clear 22.5.8. Control Register F Set 22.5.9. Event Control 22.5.10. Interrupt Control Register - Normal Mode 22.5.11. Interrupt Flag Register - Normal Mode 22.5.12. Debug Control Register - Normal Mode 22.5.13. Temporary Bits for 16-Bit Access 22.5.14. Counter Register - Normal Mode 22.5.15. Period Register - Normal Mode 22.5.16. Compare n Register - Normal Mode 22.5.17. Period Buffer Register 22.5.18. Compare n Buffer Register 22.6. Register Summary - Split Mode 22.7. Register Description - Split Mode 22.7.1. Control A - Split Mode 22.7.2. Control B - Split Mode 22.7.3. Control C - Split Mode 22.7.4. Control D - Split Mode 22.7.5. Control Register E Clear - Split Mode 22.7.6. Control Register E Set - Split Mode 22.7.7. Interrupt Control Register - Split Mode 22.7.8. Interrupt Flag Register - Split Mode 22.7.9. Debug Control Register - Split Mode 22.7.10. Low Byte Timer Counter Register - Split Mode 22.7.11. High Byte Timer Counter Register - Split Mode 22.7.12. Low Byte Timer Period Register - Split Mode 22.7.13. High Byte Period Register - Split Mode 22.7.14. Compare Register n For Low Byte Timer - Split Mode 22.7.15. High Byte Compare Register n - Split Mode 23. TCB - 16-Bit Timer/Counter Type B 23.1. Features 23.2. Overview 23.2.1. Block Diagram 23.2.2. Signal Description 23.3. Functional Description 23.3.1. Definitions 23.3.2. Initialization 23.3.3. Operation 23.3.3.1. Modes 23.3.3.1.1. Periodic Interrupt Mode 23.3.3.1.2. Time-Out Check Mode 23.3.3.1.3. Input Capture on Event Mode 23.3.3.1.4. Input Capture Frequency Measurement Mode 23.3.3.1.5. Input Capture Pulse-Width Measurement Mode 23.3.3.1.6. Input Capture Frequency and Pulse-Width Measurement Mode 23.3.3.1.7. Single-Shot Mode 23.3.3.1.8. 8-Bit PWM Mode 23.3.3.2. Output 23.3.3.3. Noise Canceler 23.3.3.4. Synchronized with Timer/Counter Type A 23.3.4. Events 23.3.5. Interrupts 23.3.6. Sleep Mode Operation 23.4. Register Summary 23.5. Register Description 23.5.1. Control A 23.5.2. Control B 23.5.3. Event Control 23.5.4. Interrupt Control 23.5.5. Interrupt Flags 23.5.6. Status 23.5.7. Debug Control 23.5.8. Temporary Value 23.5.9. Count 23.5.10. Capture/Compare 24. RTC - Real-Time Counter 24.1. Features 24.2. Overview 24.2.1. Block Diagram 24.3. Clocks 24.4. RTC Functional Description 24.4.1. Initialization 24.4.1.1. Configure the Clock CLK_RTC 24.4.1.2. Configure RTC 24.4.2. Operation - RTC 24.4.2.1. Enabling and Disabling 24.5. PIT Functional Description 24.5.1. Initialization 24.5.2. Operation - PIT 24.5.2.1. Enabling and Disabling 24.5.2.2. PIT Interrupt Timing 24.6. Events 24.7. Interrupts 24.8. Sleep Mode Operation 24.9. Synchronization 24.10. Debug Operation 24.11. Register Summary 24.12. Register Description 24.12.1. Control A 24.12.2. Status 24.12.3. Interrupt Control 24.12.4. Interrupt Flag 24.12.5. Temporary 24.12.6. Debug Control 24.12.7. Clock Selection 24.12.8. Count 24.12.9. Period 24.12.10. Compare 24.12.11. Periodic Interrupt Timer Control A 24.12.12. Periodic Interrupt Timer Status 24.12.13. PIT Interrupt Control 24.12.14. PIT Interrupt Flag 24.12.15. Periodic Interrupt Timer Debug Control 25. USART - Universal Synchronous and Asynchronous Receiver and Transmitter 25.1. Features 25.2. Overview 25.2.1. Block Diagram 25.2.2. Signal Description 25.3. Functional Description 25.3.1. Initialization 25.3.2. Operation 25.3.2.1. Frame Formats 25.3.2.2. Clock Generation 25.3.2.2.1. The Fractional Baud Rate Generator 25.3.2.3. Data Transmission 25.3.2.3.1. Disabling the Transmitter 25.3.2.4. Data Reception 25.3.2.4.1. Receiver Error Flags 25.3.2.4.2. Disabling the Receiver 25.3.2.4.3. Flushing the Receive Buffer 25.3.3. Communication Modes 25.3.3.1. Synchronous Operation 25.3.3.1.1. Clock Operation 25.3.3.1.2. External Clock Limitations 25.3.3.1.3. USART in Host SPI Mode 25.3.3.1.3.1. Frame Formats 25.3.3.1.3.2. Clock Generation 25.3.3.1.3.3. Data Transmission 25.3.3.1.3.4. Data Reception 25.3.3.1.3.5. USART in Host SPI Mode vs. SPI 25.3.3.2. Asynchronous Operation 25.3.3.2.1. Clock Recovery 25.3.3.2.2. Data Recovery 25.3.3.2.3. Error Tolerance 25.3.3.2.4. Double-Speed Operation 25.3.3.2.5. Auto-Baud 25.3.3.2.6. Half-Duplex Operation 25.3.3.2.6.1. One-Wire Mode 25.3.3.2.6.2. RS-485 Mode 25.3.3.2.7. IRCOM Mode of Operation 25.3.4. Additional Features 25.3.4.1. Parity 25.3.4.2. Start-of-Frame Detection 25.3.4.3. Multiprocessor Communication 25.3.4.3.1. Using Multiprocessor Communication 25.3.5. Events 25.3.6. Interrupts 25.4. Register Summary 25.5. Register Description 25.5.1. Receiver Data Register Low Byte 25.5.2. Receiver Data Register High Byte 25.5.3. Transmit Data Register Low Byte 25.5.4. Transmit Data Register High Byte 25.5.5. USART Status Register 25.5.6. Control A 25.5.7. Control B 25.5.8. Control C - Normal Mode 25.5.9. Control C - Host SPI Mode 25.5.10. Baud Register 25.5.11. Debug Control Register 25.5.12. IrDA Control Register 25.5.13. IRCOM Transmitter Pulse Length Control Register 25.5.14. IRCOM Receiver Pulse Length Control Register 26. SPI - Serial Peripheral Interface 26.1. Features 26.2. Overview 26.2.1. Block Diagram 26.2.2. Signal Description 26.3. Functional Description 26.3.1. Initialization 26.3.2. Operation 26.3.2.1. Host Mode Operation 26.3.2.1.1. Normal Mode 26.3.2.1.2. Buffer Mode 26.3.2.1.3. SS Pin Functionality in Host Mode - Multi-Host Support 26.3.2.2. Client Mode 26.3.2.2.1. Normal Mode 26.3.2.2.2. Buffer Mode 26.3.2.2.3. SS Pin Functionality in Client Mode 26.3.2.3. Data Modes 26.3.2.4. Events 26.3.2.5. Interrupts 26.4. Register Summary 26.5. Register Description 26.5.1. Control A 26.5.2. Control B 26.5.3. Interrupt Control 26.5.4. Interrupt Flags - Normal Mode 26.5.5. Interrupt Flags - Buffer Mode 26.5.6. Data 27. TWI - Two-Wire Interface 27.1. Features 27.2. Overview 27.2.1. Block Diagram 27.2.2. Signal Description 27.3. Functional Description 27.3.1. General TWI Bus Concepts 27.3.2. TWI Basic Operation 27.3.2.1. Initialization 27.3.2.1.1. Host Initialization 27.3.2.1.2. Client Initialization 27.3.2.2. TWI Host Operation 27.3.2.2.1. Clock Generation 27.3.2.2.2. TWI Bus State Logic 27.3.2.2.3. Transmitting Address Packets 27.3.2.2.3.1. Case M1: Address Packet Transmit Complete - Direction Bit Set to ‘0’ 27.3.2.2.3.2. Case M2: Address Packet Transmit Complete - Direction Bit Set to ‘1’ 27.3.2.2.3.3. Case M3: Address Packet Transmit Complete - Address not Acknowledged by Client 27.3.2.2.3.4. Case M4: Arbitration Lost or Bus Error 27.3.2.2.4. Transmitting Data Packets 27.3.2.2.5. Receiving Data Packets 27.3.2.3. TWI Client Operation 27.3.2.3.1. Receiving Address Packets 27.3.2.3.1.1. Case S1: Address Packet Accepted - Direction Bit Set to ‘0’ 27.3.2.3.1.2. Case S2: Address Packet Accepted - Direction Bit Set to ‘1’ 27.3.2.3.1.3. Case S3: Stop Condition Received 27.3.2.3.1.4. Case S4: Collision 27.3.2.3.2. Receiving Data Packets 27.3.2.3.3. Transmitting Data Packets 27.3.3. Additional Features 27.3.3.1. SMBus 27.3.3.2. Multi-Host 27.3.3.3. Smart Mode 27.3.3.4. Quick Command Mode 27.3.3.5. 10-Bit Address 27.3.4. Interrupts 27.3.5. Sleep Mode Operation 27.3.6. Debug Operation 27.4. Register Summary 27.5. Register Description 27.5.1. Control A 27.5.2. Debug Control 27.5.3. Host Control A 27.5.4. Host Control B 27.5.5. Host Status 27.5.6. Host Baud Rate 27.5.7. Host Address 27.5.8. Host Data 27.5.9. Client Control A 27.5.10. Client Control B 27.5.11. Client Status 27.5.12. Client Address 27.5.13. Client Data 27.5.14. Client Address Mask 28. CRCSCAN - Cyclic Redundancy Check Memory Scan 28.1. Features 28.2. Overview 28.2.1. Block Diagram 28.3. Functional Description 28.3.1. Initialization 28.3.2. Operation 28.3.2.1. Checksum 28.3.3. Interrupts 28.3.4. Sleep Mode Operation 28.3.5. Debug Operation 28.4. Register Summary - CRCSCAN 28.5. Register Description 28.5.1. Control A 28.5.2. Control B 28.5.3. Status 29. CCL - Configurable Custom Logic 29.1. Features 29.2. Overview 29.2.1. Block Diagram 29.2.2. Signal Description 29.2.3. System Dependencies 29.2.3.1. Clocks 29.2.3.2. I/O Lines 29.2.3.3. Interrupts 29.2.3.4. Debug Operation 29.3. Functional Description 29.3.1. Initialization 29.3.2. Operation 29.3.2.1. Enabling, Disabling, and Resetting 29.3.2.2. Truth Table Logic 29.3.2.3. Truth Table Inputs Selection 29.3.2.4. Filter 29.3.2.5. Edge Detector 29.3.2.6. Sequencer Logic 29.3.2.7. Clock Source Settings 29.3.3. Events 29.3.4. Sleep Mode Operation 29.3.5. Configuration Change Protection 29.4. Register Summary 29.5. Register Description 29.5.1. Control A 29.5.2. Sequencer Control 0 29.5.3. LUT n Control A 29.5.4. LUT n Control B 29.5.5. LUT n Control C 29.5.6. TRUTHn 30. AC - Analog Comparator 30.1. Features 30.2. Overview 30.2.1. Block Diagram 30.2.2. Signal Description 30.2.3. System Dependencies 30.2.3.1. Clocks 30.2.3.2. I/O Lines and Connections 30.2.3.3. Interrupts 30.2.3.4. Events 30.2.3.5. Debug Operation 30.3. Functional Description 30.3.1. Initialization 30.3.2. Operation 30.3.2.1. Input Hysteresis 30.3.2.2. Input Sources 30.3.2.2.1. Pin Inputs 30.3.2.2.2. Internal Inputs 30.3.3. Events 30.3.4. Interrupts 30.3.5. Sleep Mode Operation 30.3.6. Configuration Change Protection 30.4. Register Summary 30.5. Register Description 30.5.1. Control A 30.5.2. MUX Control A 30.5.3. Interrupt Control 30.5.4. Status 31. ADC - Analog-to-Digital Converter 31.1. Features 31.2. Overview 31.2.1. Block Diagram 31.2.2. Signal Description 31.3. Functional Description 31.3.1. Initialization 31.3.1.1. I/O Lines and Connections 31.3.2. Operation 31.3.2.1. Starting a Conversion 31.3.2.2. Clock Generation 31.3.2.3. Conversion Timing 31.3.2.4. Changing Channel or Reference Selection 31.3.2.4.1. ADC Input Channels 31.3.2.4.2. ADC Voltage Reference 31.3.2.4.3. Analog Input Circuitry 31.3.2.5. ADC Conversion Result 31.3.2.6. Temperature Measurement 31.3.2.7. Window Comparator Mode 31.3.3. Events 31.3.4. Interrupts 31.3.5. Sleep Mode Operation 31.4. Register Summary - ADCn 31.5. Register Description 31.5.1. Control A 31.5.2. Control B 31.5.3. Control C 31.5.4. Control D 31.5.5. Control E 31.5.6. Sample Control 31.5.7. MUXPOS 31.5.8. Command 31.5.9. Event Control 31.5.10. Interrupt Control 31.5.11. Interrupt Flags 31.5.12. Debug Run 31.5.13. Temporary 31.5.14. Result 31.5.15. Window Comparator Low Threshold 31.5.16. Window Comparator High Threshold 31.5.17. Calibration 32. UPDI - Unified Program and Debug Interface 32.1. Features 32.2. Overview 32.2.1. Block Diagram 32.2.2. Clocks 32.2.3. Physical Layer 32.2.4. I/O Lines and Connections 32.3. Functional Description 32.3.1. Principle of Operation 32.3.1.1. UPDI UART 32.3.1.2. BREAK Character 32.3.1.2.1. BREAK in One-Wire Mode 32.3.1.3. SYNCH Character 32.3.1.3.1. SYNCH in One-Wire Mode 32.3.2. Operation 32.3.2.1. UPDI Enabling 32.3.2.1.1. One-Wire Enable 32.3.2.1.1.1. UPDI Enable with Fuse Override of RESET Pin 32.3.2.1.1.2. UPDI Enable with High-Voltage Override of RESET Pin 32.3.2.1.1.3. Output Enable Timer Protection for GPIO Configuration 32.3.2.2. UPDI Disabling 32.3.2.2.1. Disable During Start-up 32.3.2.2.1.1. Time-Out Disable 32.3.2.2.1.2. Incorrect SYNCH pattern 32.3.2.2.2. UPDI Regular Disable 32.3.2.3. UPDI Communication Error Handling 32.3.2.4. Direction Change 32.3.3. UPDI Instruction Set 32.3.3.1. LDS - Load Data from Data Space Using Direct Addressing 32.3.3.2. STS - Store Data to Data Space Using Direct Addressing 32.3.3.3. LD - Load Data from Data Space Using Indirect Addressing 32.3.3.4. ST - Store Data from UPDI to Data Space Using Indirect Addressing 32.3.3.5. LDCS - Load Data from Control and Status Register Space 32.3.3.6. STCS - Store Data to Control and Status Register Space 32.3.3.7. REPEAT - Set Instruction Repeat Counter 32.3.3.8. KEY - Set Activation Key or Send System Information Block 32.3.4. CRC Checking of Flash During Boot 32.3.5. System Clock Measurement with UPDI 32.3.6. Inter-Byte Delay 32.3.7. System Information Block 32.3.8. Enabling of Key Protected Interfaces 32.3.8.1. Chip Erase 32.3.8.2. NVM Programming 32.3.8.3. User Row Programming 32.3.9. Events 32.3.10. Sleep Mode Operation 32.4. Register Summary 32.5. Register Description 32.5.1. Status A 32.5.2. Status B 32.5.3. Control A 32.5.4. Control B 32.5.5. ASI Key Status 32.5.6. ASI Reset Request 32.5.7. ASI Control A 32.5.8. ASI System Control A 32.5.9. ASI System Status 32.5.10. ASI CRC Status 33. Instruction Set Summary 34. Conventions 34.1. Numerical Notation 34.2. Memory Size and Type 34.3. Frequency and Time 34.4. Registers and Bits 34.4.1. Addressing Registers from Header Files 34.5. ADC Parameter Definitions 35. Electrical Characteristics 35.1. Disclaimer 35.2. Absolute Maximum Ratings 35.3. General Operating Ratings 35.4. Power Consumption 35.5. Wake-Up Time 35.6. Peripherals Power Consumption 35.7. BOD and POR Characteristics 35.8. External Reset Characteristics 35.9. Oscillators and Clocks 35.10. I/O Pin Characteristics 35.11. USART 35.12. SPI 35.13. TWI 35.14. VREF 35.15. ADC 35.16. TEMPSENSE 35.17. AC 35.18. UPDI Timing 35.19. Programming Time 36. Typical Characteristics 36.1. Power Consumption 36.1.1. Supply Currents in Active Mode 36.1.2. Supply Currents in Idle Mode 36.1.3. Supply Currents in Standby Mode 36.1.4. Supply Currents in Power-Down Mode 36.2. GPIO 36.2.1. GPIO Input Characteristics 36.2.2. GPIO Output Characteristics 36.2.3. GPIO Pull-Up Characteristics 36.3. VREF Characteristics 36.4. BOD Characteristics 36.4.1. BOD Current vs. VDD 36.4.2. BOD Threshold vs. Temperature 36.5. ADC Characteristics 36.6. TEMPSENSE Characteristics 36.7. AC Characteristics 36.8. OSC20M Characteristics 36.9. OSCULP32K Characteristics 36.10. TWI SDA Hold Timing 37. Ordering Information 37.1. Product Information 37.2. Product Identification System 38. Package Drawings 38.1. Online Package Drawings 38.2. 8-Pin SOIC 38.3. 14-Pin SOIC 38.4. 20-Pin SOIC 38.5. 20-Pin VQFN 38.6. Thermal Considerations 38.6.1. Thermal Resistance Data 38.6.2. Junction Temperature 39. Errata 39.1. Errata - ATtiny202/204/402/404/406 40. Data Sheet Revision History 40.1. Rev. A - 04/2021 40.2. Appendix - Obsolete Revision History 40.2.1. ATtiny202/402 - DS40001969 40.2.2. ATtiny204/404 - DS50002687 40.2.3. ATtiny416/816 - DS40001976 The Microchip Website Product Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service