For potential power saving both the TC and the SERCOM modules are split between PD0 and PD1. In applications where it is sufficient to use only the PD0 modules, the need for entering PD1 could be reduced, leading to a lower power consumption. The low power modules in PD0 are TC4 and SERCOM5.
As shown in Figure 1 SRAM is located in both PD1 and PD2. The low power SRAM (LP SRAM) block in PD1 is used for DMAC descriptors but can also be used to store data. Using the LP SRAM in PD1 will save power if PD2 is less frequently enabled. Another benefit from the LP SRAM is to enable DMAC transfers without slowing down other bus masters accessing the main SRAM when in Active mode.