By default all clocks except the ULP32K are switched off in Standby (STANDBY) sleep mode. Peripherals can still perform tasks as long as the Run in Standby bit in the peripheral's control register is written, e.g. Control A for the ADC module (CTRLA.RUNSTDBY written to one). This will enable the peripheral to run while in STANDBY. If in addition the clock source is set to run on demand, the oscillator will only be enabled when requested by a peripheral. STANDBY is entered by executing the WFI instruction with STANDBY written to the Sleep Mode bit group in the Sleep Configuration register (SLEEPCFG.SLEEPMODE written to 0x4). The device will exit STANDBY on any asynchronous interrupt.
In STANDBY the device will by default switch to a low power voltage regulator (LP VREG) to further reduce the power consumption. Refer to Low Power Voltage Regulator for more details. Another low power feature available while in STANDBY is the dynamical switching of power domains. Refer to Power Domains and SleepWalking with Power Domain Gating for more details.