Changing Performance Level

Switching to a different performance level does not affect oscillators, prescalers, or GCLK generators. After changing to a higher performance level it is necessary to wait for the Performance Level Ready bit in the Interrupt Flag Status and Clear register (INTFLAG.PLRDY) in the Power Manager (PM) to be set before changing the clock speed. When changing to a lower performance level the clock frequency must be set to a speed below the maximum limit before reducing performance level. It may also be necessary to change the number of read wait states, which is dependent of CPU clock speed, performance level and VDDIN voltage. Refer to the "Electrical Characteristics" chapter in the datasheet for more details. When increasing read wait states, this must apply before changing performance level. Similarly, a decrease in wait states must be done after changing perfomance level. The number of read wait states is configured by writing to the NVM Read Wait States bit group in the Control B register (CTRLB.RWS) in the Non-Volatile Memory Controller (NVMCTRL). Following are two step-by-step examples demonstrating how to change performance level.

Changing to a lower level (PL0) when running at 48MHz with VDDIN = 3.3V (> 2.7V):

  1. 1.Disable/decrease clock generators above the allowed maximum frequency at 12MHz.
  2. 2.Choose PL0 as performance level (PLCFG.PLSEL written to 0x0).
  3. 3.If the new CPU speed is <7.5MHz the number of read wait states can be reduced from one to zero (CTRLB.RWS written to 0x0)

Changing to a higher level (PL2) when running at 8MHz with VDDIN = 1.62V (< 2.7V):

  1. 1.If the new CPU speed is >28MHz the number of read wait states must be increased to two or three (CTRLB.RWS written to 0x2 or 0x3), depending on the CPU speed.
  2. 2.Choose PL2 as performance level (PLCFG.PLSEL written to 0x2).
  3. 3.Wait for the Performance Level Ready (INTFLAG.PLRDY) bit to be set. This bit change will generate an interrupt if the Performance Level Ready interrupt is enabled (INTSET.PLRDY written to one).
  4. 4.If desired, increase CPU clock speed without exceeding the maximum allowed frequency.
Parent topic: Performance Levels