Low Power Voltage Regulator

The low power voltage regulator can be used to supply VDDCORE when in Standby sleep mode if all power domains are in retention state. Refer to Power Domains for more details. If one or more power domains are active with no clocks requested, the device can still be powered by LP VREG as long as the Automatic VREG Switching Disable bit is not set (STDBYCFG.AVREGSD written to zero). Enabling this bit will force the device to be powered by the main voltage regulator as long as one or more power domains are active. The efficiency of LP VREG can be improved by setting the Low Power mode Efficiency bit in the VREG register (VREG.LPEFF written to one) for applications where a limited VDD range (2.5V to 3.6V) is used.