Voltage Scaling Control

The VDDCORE supply will change under certain circumstances, such as switching to a different performance level, entering or exiting STANDBY, or when a SleepWalking task is started. A sudden increase in VDDCORE can cause a spike in the current flow. Forcing the regulator to make a softer transition of voltage levels by writing to the Voltage Scaling Step and Voltage Scaling Frequency bit groups in the Voltage Regulator System Control register (VREG.VSSTEP and VREG.VSPER) will limit such current spike(s) but also increase the total step time. See Figure 1. The transition time can be decreased by configuring a larger voltage step height since the number of steps are reduced. By default VSVSTEP is written to zero giving a step height of 5mV. The scaling frequency VSPER determines the delay between the steps. By default VSPER is written to zero giving a delay of 1μs.

In designs where the power supply is weak, e.g. if powered by a nearly discharged battery, a softer transition may prevent the external power supply voltage level from dropping below the BOD threshold value. The current spike(s) only affects the external power supply and not the device itself, as long as the external power supply manages to source the necessary current flow.

Figure 1. Voltage Scaling