SleepWalking with Power Domain Gating

SleepWalking is a feature enabling peripherals to request clocks to perform tasks without waking the CPU, when in STANDBY. On SAM L21, this feature is extended to the capability of setting a power domain from retention to active state and vice-versa. This means that a power domain will only be active when a peripheral within needs to run. To apply this feature based on events or DMA triggers the Dynamic Power Gating bits in the Standby Configuration register (STDBYCFG.DPGPD0/1) in the Power Manager (PM) must be set. When a SleepWalking task activates a power domain, this is done without waking the CPU. When the task is complete the device can either wake up, if an interrupt is issued, or return to STANDBY.

By default, a power domain is set automatically to retention state in STANDBY if no activity is required in it. Turning on a power domain is relatively time consuming, and for some applications this delay may be unacceptable. It is then possible to disable the dynamic switching of the power domains to ensure that one or more power domains always are active in STANDBY. This feature is configured with the Power Domain Configuration bit group in the Standby Configuration register (STDBYCFG.PDCFG). Another option is to enable Linked Power Domains, allowing PD1 to be activated whenever PD0 is active, PD2 to be activated whenever PD1 is active, or activate both PD1 and PD2 if PD0 is active. This will reduce the delay if e.g. a peripheral in PD0 activates a peripheral in PD1. Linking of power domains is configured in the Linked Power Domain bit group in the Standby Configuration register (STDBYCFG.LINKPD).

Note: When a peripheral running in STANDBY is requesting a clock source, the performance level is determined by its state prior to entering STANDBY.