In SmartFusion2, IGLOO2, and RTG4 families, under specific PCIe traffic patterns, SERDES
PCIe AHBLite master interface to fabric functions improperly, requiring design
conversion to an AXI-based SERDES PCIe configuration with a new FPGA fabric-based
AXI-to-AHBLite bridge soft IP.
- An issue was discovered when using the AXI-to-AHBLite master bridge inside the PCIe
block of the SERDES.
- Under specific PCIe traffic conditions, the AXI-to-AHBLite master bridge embedded
within the SERDES block does not load its burst counter properly, which results in
early burst completions.
- Subsequently,the PCIe transaction layer packet (TLP) logic generates incorrect read
completion TLPs which will eventually result in the termination of the PCIe read TLP
completions. The system behavior during this scenario depends on the root port
used.
Traffic conditions known to cause this issue include:
- Write transactions with open read transactions.
- Read transactions with open write transactions.
For more information, see JAON-08OHTZ048.