Core Enhancements and Upgrades

The following table lists the core enhancements and upgrades. For more information about updating a core version, see section Updating a Core Version.

Table 1. Core Enhancements and Upgrades
Core 2021.2 Version Status Comments
PF_DRI 1.1.104 Production Removed the PCIe tab in the PF_DRI configurator. For information about how to reconfigure dynamically the PCIe configuration regiseters, see the PolarFire PCIe User Guide.
PF_IO 2.0.104 Production The interface was corrected when configuring input and output register modes differently.
PF_IOD_GENERIC_RX 2.1.104 Production
  • Fixed issue when using the option to expose fractional clock parallel data port.
  • Previously, IOD_GENERIC_RX with a fabric ratio of 1 generated false path constraints that did not exist in the design. These constraints have been removed.
  • Exposes eye_width_monitor port with RX_DDRX_B_G_A configuration.
PF_IOD_GENERIC_TX 2.0.111 Production See section User Control of Output Clock Port Pattern on IOD Generic Transmit Interface.
PF_IOD_TX_CCC 1.0.122 Production Repackaged with latest core version of PF_CCC.
PF_LPDDR3 2.3.113 Production See section LPDDR3 Self-refresh Entry and Exit.
PF_QDR 1.8.203 Production See section PF_QDR DOFF_N Port and Fast Simulation Enhancements.
PF_RGMII_TO_GMII 1.3.103 Production Repackaged with the latest core versions of PF_IOD_GENERIC_RX and PF_IOD_GENERIC_TX.
RTG4FCCCECALIB 2.2.005 Production See section CN19009C: Improvements to RTG4 FCCC with Enhanced PLL Calibration Core.
RTG4FDDRC 2.0.102 Production Enables fractional clock frequency.
RTG4FDDRC_INIT 2.0.102 Production Enables fractional clock frequency.
SmartFusion2/IGLOO2 FDDRC 2.0.101 Production Enables fractional clock frequency.
Parent topic: Migrating Designs to Libero SoC 2021.2