SynplifyPro and Identify

The SynplifyPro and Identify tools bundled in Libero SoC v2021.2 have been upgraded to version R-2021.03M. Besides enhancements and fixes, SynplifyPro is now fully supported on Ubuntu 18.04.

Generated names of signals and ports get renamed without special characters.

When the new attribute syn_safe_cdc is applied on a CDC path, it ensures that SynplifyPro will not add syn_preserve, syn_replicate, and syn_allow_retiming attributes, making these registers available for absorption during RAM and MATH block inference. SynplifyPro still reports the path as Safe and its description will be syn_safe_cdc attribute applied. The syn_safe_cdc can be applied on source, destination, or both. Example:
reg ar /* synthesis syn_safe_cdc = 1 */;
reg zr;
reg sync;
always @(posedge clk1)
begin
    ar <= a;
end
always @(posedge clk2)
begin
    zr <= ar;
    sync <= zr;
end
For more details, see the Synopsys FPGA Synthesis SynplifyPro ME R-2021.03M User Guide.