This customer notification applies to FPGA Static Timing Analysis (STA) data used with
Microchip's PolarFire FPGAs. As part of continuous improvement efforts, Libero SoC
v2021.2 has been updated to improve the accuracy of the PolarFire timing data in two
specific cases, described in the following section.
Prior to Libero SoC v2021.2, the two PolarFire timing paths below used delay values that
were slightly underestimated.
- Unused IP Interface Logic
Elements used as regular combinatorial logic elements have LUT4 B input to Y
output delay that was underestimated by up to 35 ps worst-case. IP Interface
Logic Elements are used to connect hard IP blocks in the FPGA fabric, such as
RAMs and Mathblocks, to user logic. When the associated hard IP blocks are
unused in a design, Libero SoC can re-use the IP Interface LUTs and SLEs for
user fabric logic. In this scenario, the 4-input LUT input B to output Y path
can be used for user logic.
- Mathblock input registers have
enable pin setup time that was underestimated by up to 77 ps worst-case.
Examples of Mathblock input register enable pins are
A_EN,
B_EN, C_EN, and
D_EN.
For more information, see CYER-05NWLS164.