Libero SoC v2021.2 includes the first general release of Smart High-Level Synthesis (SmartHLS) tool.
SmartHLS is an Eclipse-based integrated development environment that accepts C++ software code as input and generates a SmartDesign IP component (Verilog HDL) as output. Hardware engineers can instantiate the generated SmartDesign IP component in the SmartDesign canvas available in Libero SoC design suite to build an FPGA system.
The SmartHLS software requires a free license that you can request in the Microsemi SoC Portal. Use the following procedure to request the free license.
license.dat
file will be emailed to you, enabling
you to use SmartHLS.SmartHLS license.dat
file, open it, copy
the content, and add it to your existing Libero software license file with the
similar Libero license option (Disk ID or MAC ID). For example, if you generated
a node locked license for the SmartHLS tool, add the SmartHLS license file
content to the Libero node locked license.
SmartHLS-2021.2/docs/releasenotes.html
.