CN19009C: Improvements to RTG4 FCCC with Enhanced PLL Calibration Core

With Libero SoC v2021.2, the RTG4 FCCC with Enhanced PLL Calibration core will be updated to improve robustness in various user configurations. The following changes are being implemented:

• Update the PLL_ARST_N input to PLL_RST_N and default to synchronous relationship with CLK_50MHZ, with a user option to revert to asynchronous assertion.
• Add PLL_RST_N reset release synchronization to ensure that reset release is always synchronous to CLK_50MHZ.
• Convert all resets internal to the PLL calibration soft IP into synchronous resets.
• Add synthesis directives to preserve/keep the PLL calibration soft IP's FSM state register and illegal state detection logic.
• Enable Single-Event Transient (SET) mitigation for all Flip-Flops (FFs) in each core instance via a Netlist Design Constraint (.NDC).
• When user dynamic configuration is enabled, drive the APB configuration interface with CLK_50MHZ input and remove option for a separate, user-supplied APB_S_PCLK input.
• Add a 500us timeout counter on the PLL calibration soft IPs LOCK_WAIT FSM state.