The PolarFire XCVR can source three different clocks into the fabric:
TX_CLK
RX_CLK
REFCLK
(FAB_REF_CLK
)These clocks contain high-frequency jitter that is not automatically considered by Libero in the timing report and SmartTime. It is recommended that users add clock-uncertainty constraints to these clocks in their design. The following table shows recommended values for clock uncertainty per clock, resource, and speed-grade.
Clock Type | STD | -1 |
---|---|---|
FAB_REF_CLK on Global |
275 ps | 200 ps |
FAB_REF_CLK on Regional |
N/A | N/A |
TX_CLK_G on Global |
300 ps | 225 ps |
TX_CLK_R on Regional |
225 ps | 150 ps |
RX_CLK_G on Global |
325 ps | 250 ps |
RX_CLK_R on Regional |
250 ps | 175 ps |
set_clock_uncertainty -setup 0.150 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/TX_CLK_R } ]
set_clock_uncertainty -setup 0.175 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/RX_CLK_R } ]
The following example shows a clock-uncertainty constraint with STD speed grade.
# TX_CLK and RX_CLK on Globals
set_clock_uncertainty -setup 0.300 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/TX_CLK_G } ]
set_clock_uncertainty -setup 0.325 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/RX_CLK_G } ]
# FAB_REF_CLK on Global
set_clock_uncertainty -setup 0.275 [get_clocks PF_DDR4_C0_0/CCC_0/pll_inst_0/OUT1]
The automatic management of these constraints will be added in a future release of Libero SoC.