| D |
02/2022 |
- Added data sheet
clarifications:
- Updated data
sheet clarifications:
|
| C |
10/2021 |
- Updated
errata:
- Device:
Some Reserved Fuse Bits Are ‘
1’
- Device:
CRC Check During Reset Initialization Is Not
Functional
- USART:
Start-of-Frame Detection Can Unintentionally Be
Enabled in Active Mode When RXCIF Is
‘
0’
- Added errata:
- CLKCTRL:
PLL Status Not Working as Expected
- DAC: DAC Output Buffer Lifetime Drift
- NVMCTRL: Flash Multi-Page Erase Can Erase Write
Protected Section
- TCD:
Halting TCD and Wait for SW Restart Does Not Work
if Compare Value A Is
0 or Dual
Slope Mode Is Used
- TWI:
Flush Nonfunctional
|
| B |
11/2020 |
- Add new device
revision (A4)
- Added errata:
- Device:
Some Reserved Fuse Bits Are ‘
1’
- Device:
CRC Check During Reset Initialization Is Not
Functional
- CCL:
The LINK Input Source Selection for LUT3 Is Not
Functional on 28- and 32-Pin Device
- RSTCTRL:
BOD Registers Not Reset When UPDI Is
Enabled
- TCA:
Restart Will Reset Counter Direction in NORMAL
and FRQ Mode
- TCB:
CCMP and CNT Registers Operate as 16-Bit
Registers in 8-Bit PWM Mode
- TCD:
Asynchronous Input Events Not Working When TCD
Counter Prescaler Is Used
- USART:
Start-of-Frame Detection Can Unintentionally Be
Enabled in Active Mode When RXCIF Is
‘
0’
|
| A |
06/2020 |
Initial document release |