Interrupt Control
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIGOVR | SAMPOVR | RESOVR | WCMP | SAMPRDY | RESRDY | ||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Trigger Overrun Interrupt Enable
This bit controls whether the interrupt for a trigger overrun is enabled or not.
Value | Description |
---|---|
0 | The Trigger Overrun interrupt is disabled |
1 | The Trigger Overrun interrupt is enabled |
Sample Overwrite Interrupt Enable
This bit controls whether the interrupt for a sample overwrite is enabled or not.
Value | Description |
---|---|
0 | The Sample Overwrite interrupt is disabled |
1 | The Sample Overwrite interrupt is enabled |
Result Overwrite Interrupt Enable
This bit controls whether the interrupt for a result overwrite is enabled or not.
Value | Description |
---|---|
0 | The Result Overwrite interrupt is disabled |
1 | The Result Overwrite interrupt is enabled |
Window Comparator Interrupt Enable
This bit controls whether the interrupt for the Window Comparator is enabled or not.
Value | Description |
---|---|
0 | The Window Comparator interrupt is disabled |
1 | The Window Comparator interrupt is enabled |
Sample Ready Interrupt Enable
This bit controls whether the Sample Ready interrupt is enabled or not.
Value | Description |
---|---|
0 | The Sample Ready interrupt is disabled |
1 | The Sample Ready interrupt is enabled |
Result Ready Interrupt Enable
This bit controls whether the Result Ready interrupt is enabled or not.
Value | Description |
---|---|
0 | The Result Ready interrupt is disabled |
1 | The Result Ready interrupt is enabled |