ATtiny1624/1626/1627

MCLKLOCK

Main Clock Lock

  0x02 8 Configuration Change Protection Based on OSCLOCK in FUSE.OSCCFG    

Main Clock Lock

Bit  7 6 5 4 3 2 1 0  
                LOCKEN  
Access                R/W  
Reset                x  

Bit 0 – LOCKEN: Lock Enable

Lock Enable

Writing this bit to ‘1’ will lock the CLKCTRL.MCLKCTRLA and CLKCTRL.MCLKCTRLB registers, and, if applicable, the calibration settings for the current main clock source from further software updates. Once locked, the CLKCTRL.MCLKLOCK registers cannot be accessed until the next hardware Reset.

This provides protection for the CLKCTRL.MCLKCTRLA and CLKCTRL.MCLKCTRLB registers and calibration settings for the main clock source from unintentional modification by software.

At Reset, the LOCKEN bit is loaded based on the OSCLOCK bit in FUSE.OSCCFG.