LUT n Control A
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EDGEDET | OUTEN | FILTSEL[1:0] | CLKSRC[2:0] | ENABLE | |||
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Edge Detection
| Value | Description |
|---|---|
| 0 | Edge detector is disabled |
| 1 | Edge detector is enabled |
Output Enable
1’, the pin
configuration of the PORT I/O-Controller is overridden.| Value | Description |
|---|---|
| 0 | Output to pin disabled |
| 1 | Output to pin enabled |
Filter Selection
These bits select the LUT output filter options.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Filter disabled |
| 0x1 | SYNCH | Synchronizer enabled |
| 0x2 | FILTER | Filter enabled |
| 0x3 | - | Reserved |
Clock Source Selection
This bit selects between various clock sources to be used as the clock (CLK_LUTn) for an LUT.
The CLK_LUTn of the even LUT is used for clocking the sequencer of an LUT pair.
| Value | Name | Description |
|---|---|---|
0x0 |
CLKPER | CLK_PER is clocking the LUT |
0x1 |
IN2 | LUTn-TRUTHSEL[2] is clocking the LUT |
0x2 |
- | Reserved |
0x3 |
- | Reserved |
0x4 |
OSC20M | 20 MHz oscillator before prescaler is clocking the LUT |
0x5 |
OSCULP32K | 32.768 kHz internal oscillator is clocking the LUT |
0x6 |
OSCULP1K | 1.024 kHz (OSCKULP32K after DIV32) is clocking the LUT |
0x7 |
- | Reserved |
LUT Enable
| Value | Description |
|---|---|
| 0 | The LUT is disabled |
| 1 | The LUT is enabled |