ATtiny1624/1626/1627

LUTnCTRLA

LUT n Control A

  0x08 + n*0x04 [n=0..3] 8 Enable-Protected 0x00   4 4 0,1,2,3,4,5,6,7 n

LUT n Control A

Bit  7 6 5 4 3 2 1 0  
  EDGEDET OUTEN FILTSEL[1:0] CLKSRC[2:0] ENABLE  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bit 7 – EDGEDET: Edge Detection

Edge Detection

ValueDescription
0 Edge detector is disabled
1 Edge detector is enabled

Bits 3:1 – CLKSRC[2:0]: Clock Source Selection

Clock Source Selection

This bit selects between various clock sources to be used as the clock (CLK_LUTn) for an LUT.

The CLK_LUTn of the even LUT is used for clocking the sequencer of an LUT pair.

Value Name Description
0x0 CLKPER CLK_PER is clocking the LUT
0x1 IN2 LUTn-TRUTHSEL[2] is clocking the LUT
0x2 - Reserved
0x3 - Reserved
0x4 OSC20M 20 MHz oscillator before prescaler is clocking the LUT
0x5 OSCULP32K 32.768 kHz internal oscillator is clocking the LUT
0x6 OSCULP1K 1.024 kHz (OSCKULP32K after DIV32) is clocking the LUT
0x7 - Reserved

Bits 5:4 – FILTSEL[1:0]: Filter Selection

Filter Selection

These bits select the LUT output filter options.

ValueNameDescription
0x0 DISABLE Filter disabled
0x1 SYNCH Synchronizer enabled
0x2 FILTER Filter enabled
0x3 - Reserved

Bit 6 – OUTEN: Output Enable

Output Enable

This bit enables the LUT output to the LUTn OUT pin. When written to ‘1’, the pin configuration of the PORT I/O-Controller is overridden.
ValueDescription
0 Output to pin disabled
1 Output to pin enabled

Bit 0 – ENABLE: LUT Enable

LUT Enable

ValueDescription
0 The LUT is disabled
1 The LUT is enabled