Events

The CCL can generate the events shown in the table below.

Table 1. Event Generators in the CCL
Generator Name				Description	Event Type	Generating Clock Domain	Length of Event
Peripheral			Event	Description	Event Type	Generating Clock Domain	Length of Event
CCL			LUTn	LUT output level	Level	Asynchronous	Depends on the CCL configuration

The CCL has the event users below for detecting and acting upon input events.

Table 2. Event Users in the CCL
User Name		Description	Input Detection	Async/Sync
Peripheral	Input	Description	Input Detection	Async/Sync
CCL	LUTnx	LUTn input x or clock signal	No detection	Async

The event signals are passed directly to the LUTs without synchronization or input detection logic.

Two event users are available for each LUT. They can be selected as LUTn inputs by writing to the INSELn bit groups in the LUT n Control B and Control C (CCL.LUTnCTRLB or LUTnCTRLC) registers.

Refer to the EVSYS - Event System section for more details regarding the event types and the EVSYS configuration.

ATtiny1624/1626/1627

Events