Timer synchronization and output logic level are dependent on the selected Timer Mode (CNTMODE) bit field in Control B (TCBn.CTRLB) register. In Single-Shot mode, the timer/counter can be configured so that the signal generation happens asynchronously to an incoming event (ASYNC = 1 in TCBn.CTRLB). The output signal is then set immediately at the incoming event instead of being synchronized to the TCB clock. Even though the output is set immediately, it will take two to three CLK_TCB cycles before the counter starts counting.

Writing the Compare/Capture Output Enable (CCMPEN) bit in TCBn.CTRLB to ‘1’ enables the waveform output. This will make the waveform output available on the corresponding pin, overriding the value in the corresponding PORT output register.

The different configurations and their impact on the output are listed in the table below.
Table 1. Output Configuration
1 Single-Shot mode 0 The output is high when the counter starts, and the output is low when the counter stops
1 The output is high when the event arrives, and the output is low when the counter stops
8-bit PWM mode Not applicable 8-bit PWM mode
Other modes Not applicable The Compare/Capture Pin Initial Value bit (CCMPINIT) in the Control B (TCBn.CTRLB) register selects the initial output level
0 Not applicable Not applicable No output

It is not recommended to change modes while the peripheral is enabled, as this can produce an unpredictable output. There is a possibility that an interrupt flag is set during the timer configuration. It is recommended to clear the Timer/Counter Interrupt Flags (TCBn.INTFLAGS) register after configuring the peripheral.