ATtiny1624/1626/1627

ASI_CTRLA

ASI Control A

  0x09 8 - 0x03    

ASI Control A

Bit  7 6 5 4 3 2 1 0  
              UPDICLKSEL[1:0]  
Access              R/W R/W  
Reset              1 1  

Bits 1:0 – UPDICLKSEL[1:0]: UPDI Clock Divider Select

UPDI Clock Divider Select

Writing these bits selects the UPDI clock output frequency. The default setting after Reset and enable is 4 MHz. Any other clock output selection is only recommended when the BOD is at the highest level. For all other BOD settings, the default 4 MHz selection is recommended.

ValueDescription
0x0 Reserved
0x1 16 MHz UPDI clock
0x2 8 MHz UPDI clock
0x3 4 MHz UPDI clock (Default Setting)