Control Register E Clear - Split Mode

Use this register instead of a Read-Modify-Write (RMW) to clear individual bits by writing a ‘1’ to its bit location.

  0x04 8 - 0x00    

Control Register E Clear - Split Mode

Bit  7 6 5 4 3 2 1 0  
          CMD[1:0] CMDEN[1:0]  
Access          R/W R/W R/W R/W  
Reset          0 0 0 0  

Bits 3:2 – CMD[1:0]: Command


This bit field is used for software control of restart and reset of the timer/counter. The command bit field is always read as ‘0’.

0x0 NONE No command
0x1 - Reserved
0x2 RESTART Force restart
0x3 RESET Force hard Reset (ignored if the timer/counter is enabled)

Bits 1:0 – CMDEN[1:0]: Command Enable

Command Enable

This bit field configures what timer/counters the command given by the CMD-bits will be applied to.

0x0 NONE None
0x1 - Reserved
0x2 - Reserved
0x3 BOTH Command (CMD) will be applied to both low byte and high byte timer/counter