1
’. The BUFWR bit in SPIn.CTRLB does not affect Host mode. In Buffer
mode, the system is double-buffered in the transmit direction and triple-buffered in the
receive direction. This influences the data handling in the following ways:When both the shift register and the Transmit Data Buffer register become empty, the Transfer Complete Interrupt Flag (TXCIF) in the Interrupt Flags (SPIn.INTFLAGS) register will be set. This will cause the corresponding interrupt to be executed if this interrupt and the global interrupts are enabled. Setting the Transfer Complete Interrupt Enable (TXCIE) in the Interrupt Control (SPIn.INTCTRL) register enables the Transfer Complete Interrupt.