ATtiny1624/1626/1627

ADC Clock

The ADC clock (CLK_ADC) is scaled down from the peripheral clock (CLK_PER). This can be configured by the Prescaler (PRESC) bit field in the Control B (ADCn.CTRLB) register. The PGA Bias Select (PGABIASSEL) bit field in the PGA Control (ADCn.PGACTRL) register can be configured to reduce PGA power consumption depending on the ADC clock frequency.

Some of the internal timings in the ADC and the PGA are independent of CLK_ADC. To ensure correct internal timing regardless of the ADC clock frequency, a 1 ┬Ás timebase, given in CLK_PER cycles, must be written to the TIMEBASE bit field in the Control C (ADCn.CTRLC) register.

The timebase must be rounded up to the closest integer. The following code snippet shows how this can be done using the ceil function.

#include <math.h>
#define CLK_PER 3333333ul // 20 MHz/6 = 3.333333 MHz
#define TIMEBASE_VALUE ((uint8_t) ceil(CLK_PER*0.000001))