Peripheral Address Map

The address map shows the base address for each peripheral. For complete register description and summary for each peripheral, refer to the respective peripheral sections.

Table 1. Peripheral Address Map
Base Address	Name	Description
`0x0000`	VPORTA	Virtual Port A
`0x0004`	VPORTB	Virtual Port B
`0x0008`	VPORTC	Virtual Port C
`0x001C`	GPIO	General Purpose I/O registers
`0x0030`	CPU	CPU
`0x0040`	RSTCTRL	Reset Controller
`0x0050`	SLPCTRL	Sleep Controller
`0x0060`	CLKCTRL	Clock Controller
`0x0080`	BOD	Brown-out Detector
`0x00A0`	VREF	Voltage Reference
`0x0100`	WDT	Watchdog Timer
`0x0110`	CPUINT	Interrupt Controller
`0x0120`	CRCSCAN	Cyclic Redundancy Check Memory Scan
`0x0140`	RTC	Real-Time Counter
`0x0180`	EVSYS	Event System
`0x01C0`	CCL	Configurable Custom Logic
`0x0400`	PORTA	Port A Configuration
`0x0420`	PORTB	Port B Configuration
`0x0440`	PORTC	Port C Configuration
`0x05E0`	PORTMUX	Port Multiplexer
`0x0600`	ADC0	Analog-to-Digital Converter
`0x0680`	AC0	Analog Comparator 0
`0x0800`	USART0	Universal Synchronous Asynchronous Receiver Transmitter 0
`0x0820`	USART1	Universal Synchronous Asynchronous Receiver Transmitter 1
`0x08A0`	TWI0	Two-Wire Interface
`0x08C0`	SPI0	Serial Peripheral Interface
`0x0A00`	TCA0	Timer/Counter Type A instance 0
`0x0A80`	TCB0	Timer/Counter Type B instance 0
`0x0A90`	TCB1	Timer/Counter Type B instance 1
`0x0F00`	SYSCFG	System Configuration
`0x1000`	NVMCTRL	Nonvolatile Memory Controller

Table 2. System Memory Address Map
Base Address	Name	Description
`0x1100`	SIGROW	Signature Row
`0x1280`	FUSE	Device specific fuses
`0x128A`	LOCKBIT	Lock bits
`0x1300`	USERROW	User Row

ATtiny1624/1626/1627

Peripheral Address Map