The LDS instruction is used to load data from the system bus into
the PHY layer shift register for serial readout. The LDS instruction is
based on direct addressing, and the address must be given as an operand to the
instruction for the data transfer to start. The maximum supported size for the address
and data is 32 bits. The LDS instruction supports repeated memory
access when combined with the REPEAT instruction.
After issuing the LDS instruction, the number of desired
address bytes, as indicated by the Size A field followed by the output data size, which
is selected by the Size B field, must be transmitted. The output data is issued after
the specified Guard Time (GT). When combined with the REPEAT
instruction, the address must be sent in for each iteration of the repeat, meaning after
each time the output data sampling is done. There is no automatic address increment when
using REPEAT with LDS, as it uses a direct addressing
protocol.
LDS Instruction
Operation
When the instruction is decoded, and the address byte(s) are received as dictated by the decoded instruction, the DL layer will synchronize all required information to the ACC layer, which will handle the bus request and synchronize data buffered from the bus back again to the DL layer. This will create a synchronization delay that must be taken into consideration upon receiving the data from the UPDI.