ATtiny1624/1626/1627

MDATA

Host Data

  0x08 8 - 0x00    

Host Data

Bit  7 6 5 4 3 2 1 0  
  DATA[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 7:0 – DATA[7:0]: Data

Data

This bit field provides direct access to the host’s physical shift register, which is used to shift out data on the bus (transmit) and to shift in data received from the bus (receive). The direct access implies that the MDATA register cannot be accessed during byte transmissions.

Reading valid data or writing data to be transmitted can only be successful when the CLKHOLD bit is read as ‘1’ or when an interrupt occurs.

A write access to the MDATA register will command the host to perform a byte transmit operation on the bus, directly followed by receiving the Acknowledge bit from the client. This is independent of the Acknowledge Action (ACKACT) bit from the Host Control B (TWIn.MCTRLB) register. The write operation is performed regardless of winning or losing arbitration before the Write Interrupt Flag (WIF) is set to ‘1’.

If the Smart Mode Enable (SMEN) bit in the Host Control A (TWIn.MCTRLA) register is set to ‘1’, a read access to the MDATA register will command the host to perform an acknowledge action. This is dependent on the setting of the Acknowledge Action (ACKACT) bit from the Host Control B (TWIn.MCTRLB) register.

Notes:
  1. 1.The WIF and RIF flags are cleared automatically if the MDATA register is read while ACKACT is set to ‘1’.
  2. 2.The ARBLOST and BUSEER flags are left unchanged.
  3. 3.The WIF, RIF, ARBLOST, and BUSERR flags together with the Clock Hold (CLKHOLD) bit are all located in the Host Status (TWIn.MSTATUS) register.