ATtiny1624/1626/1627

CTRLC

Control C

  0x02 8 - 0x00    

Control C

Bit  7 6 5 4 3 2 1 0  
  TIMEBASE[4:0] REFSEL[2:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 7:3 – TIMEBASE[4:0]: Timebase

Timebase

This bit field controls the CLK_PER cycles to get a period equal to or larger than 1 µs. This is used for timing internal delays in the ADC before starting a conversion, such as a guard time between changing input reference or PGA gain settings.

Bits 2:0 – REFSEL[2:0]: Reference Selection

Reference Selection

This bit field controls the voltage reference for the ADC. Changing to one of the internal references will require a 60 µs initialization time.

Note: The internal references can only be used if lower than VDD - 0.5V.
ValueNameDescription
0x0 VDD VDD
0x1 - Reserved
0x2 VREFA External reference VREFA
0x3 - Reserved
0x4 1024MV Internal reference 1.024V
0x5 2048MV Internal reference 2.048V
0x6 2500MV Internal reference 2.500V
0x7 4096MV Internal reference 4.096V