Event Generators

Each event channel has several possible event generators, but only one can be selected at a time. The event generator for a channel is selected by writing to the respective Channel n Generator Selection (EVSYS.CHANNELn) register. By default, the channels are not connected to any event generator. For details on event generation, refer to the documentation of the corresponding peripheral.

A generated event is either synchronous or asynchronous to the device peripheral clock (CLK_PER). Asynchronous events can be generated outside the normal edges of the peripheral clock, making the system respond faster than the selected clock frequency would suggest. Asynchronous events can also be generated while the device is in a sleep mode when the peripheral clock is not running.

Any generated event is classified as either a pulse event or a level event. In both cases, the event can be either synchronous or asynchronous, with properties according to the table below.

Table 1. Properties of Generated Events
Event Type	Sync/Async	Description
Pulse	Sync	An event generated from CLK_PER that lasts one clock cycle
Pulse	Async	An event generated from a clock other than CLK_PER lasting one clock cycle
Level	Sync	An event generated from CLK_PER that lasts multiple clock cycles
Level	Async	An event generated without a clock (for example, a pin or a comparator), or an event generated from a clock other than CLK_PER that lasts multiple clock cycles

The properties of both the generated event and the intended event user must be considered in order to ensure reliable and predictable operation.

The table below shows the available event generators for this device family.

Generator Name		Description	Event Type	Generating Clock Domain	Length of Event
Peripheral	Event	Description	Event Type	Generating Clock Domain	Length of Event
UPDI	SYNCH	SYNCH character	Level	CLK_UPDI	SYNCH character on UPDI RX input synchronized to CLK_UPDI
RTC	OVF	Overflow	Pulse	CLK_RTC	One CLK_RTC period
	CMP	Compare Match	Pulse		One CLK_RTC period
	PIT_DIV8192	Prescaled RTC clock divided by 8192	Level		Given by prescaled RTC clock divided by 8192
	PIT_DIV4096	Prescaled RTC clock divided by 4096			Given by prescaled RTC clock divided by 4096
	PIT_DIV2048	Prescaled RTC clock divided by 2048			Given by prescaled RTC clock divided by 2048
	PIT_DIV1024	Prescaled RTC clock divided by 1024			Given by prescaled RTC clock divided by 1024
	PIT_DIV512	Prescaled RTC clock divided by 512			Given by prescaled RTC clock divided by 512
	PIT_DIV256	Prescaled RTC clock divided by 256			Given by prescaled RTC clock divided by 256
	PIT_DIV128	Prescaled RTC clock divided by 128			Given by prescaled RTC clock divided by 128
	PIT_DIV64	Prescaled RTC clock divided by 64			Given by prescaled RTC clock divided by 64
CCL	LUTn	LUT output level	Level	Asynchronous	Depends on CCL configuration
ACn	OUT	Comparator output level	Level	Asynchronous	Given by AC output level
ADCn	RES	Result ready	Pulse	CLK_PER	One CLK_PER period
	SAMP	Sample ready
	WCMP	Window compare match
PORTx	PINn	Pin level	Level	Asynchronous	Given by pin level
USARTn	XCK	USART Baud clock	Level	CLK_PER	Minimum two CLK_PER periods
SPIn	SCK	SPI Host clock	Level	CLK_PER	Minimum two CLK_PER periods
TCAn	OVF_LUNF	Normal mode: Overflow Split mode: Low Byte Timer underflow	Pulse	CLK_PER	One CLK_PER period
	HUNF	Normal mode: Not available Split mode: High Byte Timer underflow	Pulse	CLK_PER	One CLK_PER period
	CMP0_LCMP0	Normal mode: Compare Channel 0 match Split mode: Low Byte Timer Compare Channel 0 match	Pulse	CLK_PER	One CLK_PER period
	CMP1_LCMP1	Normal mode: Compare Channel 1 match Split mode: Low Byte Timer Compare Channel 1 match	Pulse	CLK_PER	One CLK_PER period
	CMP2_LCMP2	Normal mode: Compare Channel 2 match Split mode: Low byte timer Compare Channel 2 match	Pulse	CLK_PER	One CLK_PER period
TCBn	CAPT	CAPT flag set	Pulse	CLK_PER	One CLK_PER period
TCBn	OVF	OVF flag set	Pulse	CLK_PER	One CLK_PER period

ATtiny1624/1626/1627

Event Generators