ATtiny1624/1626/1627

INTFLAGS

Interrupt Flags

  0x05 8 - 0x00    

Interrupt Flags

Bit  7 6 5 4 3 2 1 0  
      TRIGOVR SAMPOVR RESOVR WCMP SAMPRDY RESRDY  
Access      R/W R/W R/W R/W R/W R/W  
Reset      0 0 0 0 0 0  

Bit 5 – TRIGOVR: Trigger Overrun Interrupt Flag

Trigger Overrun Interrupt Flag

This flag is cleared by writing a ‘1’ to it.

This flag is set when a start trigger is received while a conversion is ongoing.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Trigger Overrun interrupt flag.

Bit 4 – SAMPOVR: Sample Overwrite Interrupt Flag

Sample Overwrite Interrupt Flag

This flag is cleared by writing a ‘1’ to it.

This flag is set when an unread sample is overwritten in the Sample (ADCn.SAMPLE) register.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Sample Overwrite interrupt flag.

Bit 3 – RESOVR: Result Overwrite Interrupt Flag

Result Overwrite Interrupt Flag

This flag is cleared by writing a ‘1’ to it.

This flag is set when an unread result is overwritten in the Result (ADCn.RESULT) register.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Result Overwrite interrupt flag.

Bit 2 – WCMP: Window Comparator Interrupt Flag

Window Comparator Interrupt Flag

This flag is cleared by writing a ‘1’ to it.

This flag is set when the conversion or accumulation is complete, and the thresholds match the selected window comparator source and mode, as set by WINSRC and WINCM in the Control D (ADCn.CTRLD) register.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Window Comparator interrupt flag.

Bit 1 – SAMPRDY: Sample Ready Interrupt Flag

Sample Ready Interrupt Flag

This flag is cleared by writing a ‘1’ to it or by reading the Sample (ADCn.SAMPLE) register.

This flag is set when a conversion is complete, and a new sample is ready.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Sample Ready interrupt flag.

Bit 0 – RESRDY: Result Ready Interrupt Flag

Result Ready Interrupt Flag

This flag is cleared by writing a ‘1’ to it or by reading the Result (ADCn.RESULT) register.

This flag is set when a conversion or accumulation is complete, and a new result is ready.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Result Ready interrupt flag.