PGA Control
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GAIN[2:0] | PGABIASSEL[1:0] | ADCPGASAMPDUR[1:0] | PGAEN | ||||
AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Reset0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
GAIN
Value | Name | Description |
---|---|---|
0x0 | 1X | 1x gain |
0x1 | 2X | 2x gain |
0x2 | 4X | 4x gain |
0x3 | 8X | 8x gain |
0x4 | 16X | 16x gain |
Other | - | Reserved |
PGA Bias Select
Value | Name | Description |
---|---|---|
0x0 |
1X | 100% BIAS current. Usable for fCLK_ADC ≤ 6 MHz. |
0x1 |
3_4X | 75% BIAS current. Usable for fCLK_ADC ≤ 4 MHz. |
0x2 |
1_2X | 50% BIAS current. Usable for fCLK_ADC ≤ 2.5 MHz. |
0x3 |
1_4X | 25% BIAS current. Usable for fCLK_ADC ≤ 1.25 MHz. |
ADC PGA Sample Duration
Value | Name | Description |
---|---|---|
0x0 |
6CLK | 6 CLK_ADC cycles. Usable for fCLK_ADC ≤ 1.25 MHz. |
0x1 |
15CLK | 15 CLK_ADC cycles. Usable for fCLK_ADC ≤ 5 MHz. |
|
20CLK | 20 CLK_ADC cycles. Usable for fCLK_ADC ≤ 6 MHz. |
0x3 |
- | Reserved |
PGA Enable
This bit controls whether the PGA is enabled or not when selected by the VIA bit field in the Input Multiplexer (ADCn.MUXPOS or ADCn.MUXNEG) registers.
1
’, the PGA will be ON continuously, even when not
selected by the VIA bit field. This eliminates the initialization time if
reconfiguring the ADC to use the PGA.Value | Description |
---|---|
0 | The PGA is disabled |
1 | The PGA is enabled |