ATtiny1624/1626/1627

Output Formats

The output from an ADC conversion is given by the following equations:

Single-Ended 12-bit conversion=VINP×GainVREF×4096∈[0,4095]
Single-Ended 8-bit conversion=VINP×GainVREF×256∈[0,255]
Differential 12-bit conversion=(VINP−VINN)×GainVREF×2048∈[-2048,2047]
Differential 8-bit conversion=(VINP−VINN)×GainVREF×128∈[-128,127]

Where VINP and VINN are the positive and negative inputs to the ADC, and VREF is the selected voltage reference. The gain is between 1x and 16x as configured in the PGA, and 1x if the PGA is not in use.

The ADC has two output registers, the Sample (ADCn.SAMPLE) and Result (ADCn.RESULT) registers. The 16-bit Sample register will always be updated with the latest ADC conversion output (one sample). All accumulation modes will accumulate samples in an internal sample accumulator, configured by the Sample Accumulation Number Select (SAMPNUM) bit field in the Control F (ADCn.CTRLF) register. The sample accumulator is sufficiently wide to avoid overflow for all supported accumulation configurations, and the accumulated result is automatically transferred to the 32-bit Result register at the end of a Burst or Series mode accumulation. In single conversion modes, the Result register will be updated with the latest sample, identical to the Sample register.

Operating modes with scaling can be selected to limit the accumulated result to 16 bits of resolution if more than 16 samples are accumulated. Scaling is always applied after accumulating the last sample in Burst or Series modes and is carried out by right shifting the accumulated result by SAMPNUM-4 bits.

The Left Adjust (LEFTADJ) bit in the Control F register enables left shift of the output data in the modes where this is supported. If enabled, this will left shift the output from both the Result and the Sample registers.

The data format for a sample in Single-Ended mode is an unsigned number, where 0x0000 represents zero, and 0x0FFF represents the largest number (full scale). If the analog input is higher than the reference level of the ADC, the 12-bit ADC output will be equal the maximum value of 0x0FFF. Likewise, if the input is below 0V, the ADC output will be 0x0000. For Differential mode, the data format is two's complement, with sign extension.

The following tables show the Result register output formats for single-ended and differential conversions, by mode of operation and left adjustment.

Table 1. RESULT Register - Single-Ended Mode
MODE LEFTADJ RES[31:24] RES[23:16] RES[15:12] RES[11:8] RES[7:0]
0 X(1) 0x00 Conversion[7:0]
1 0 0x00 Conversion[11:0]
1 0x00 Conversion[11:0] << 4
2, 4 X(1) 0x00 Accumulation[23:0]
3, 5 0 0x00 Scaled accumulation[15:0]
1 0x00 Scaled accumulation[15:0](2)
Notes:
  1. 1.Left adjust is not available in 8-bit mode or accumulation modes without scaling.
  2. 2.If SAMPNUM < 4, the result is left-shifted 4-SAMPNUM bits such that bit 15 is the MSb.
Table 2. RESULT Register - Differential Mode
MODE LEFTADJ RES[31:24] RES[23:16] RES[15:12] RES[11:8] RES[7:0]
0 X(1) Sign extension Signed conversion[7:0]
1 0 Sign extension Signed conversion[11:0]
1 Sign extension Signed conversion[11:0] << 4
2, 4 X(1) Sign extension Signed accumulation[23:0]
3, 5 0 Sign extension Signed scaled accumulation[15:0]
1 Sign extension Signed scaled accumulation[15:0](2)
Notes:
  1. 1.Left adjust is not available in 8-bit mode or accumulation modes without scaling.
  2. 2.If SAMPNUM < 4, the result is left-shifted 4-SAMPNUM bits such that bit 15 is the MSb.

The following table shows the Sample register output formats by mode of operation, left adjustment, and Differential or Single-Ended conversions.

Table 3. SAMPLE Register
MODE LEFTADJ DIFF SAMPLE[15:12] SAMPLE[11:8] SAMPLE[7:0]
0 X 0 0x00 Conversion[7:0]
1 Sign extension Signed conversion[7:0]
Other 0 0 0x00 Conversion[11:0]
1 Sign extension Signed conversion[11:0]
1 0 Conversion[11:0] << 4
1 Signed conversion[11:0] << 4
Parent topic: Operation