ATtiny1624/1626/1627

INTFLAGS

Interrupt Flag Register - Split Mode

  0x0B 8 - 0x00    

Interrupt Flag Register - Split Mode

Bit  7 6 5 4 3 2 1 0  
    LCMP2 LCMP1 LCMP0     HUNF LUNF  
Access    R/W R/W R/W     R/W R/W  
Reset    0 0 0     0 0  

Bit 6 – LCMP2: Low byte Compare Channel 2 Interrupt Flag

Low byte Compare Channel 2 Interrupt Flag

See LCMP0 flag description.

Bit 5 – LCMP1: Low byte Compare Channel 1 Interrupt Flag

Low byte Compare Channel 1 Interrupt Flag

See LCMP0 flag description.

Bit 4 – LCMP0: Low byte Compare Channel 0 Interrupt Flag

Low byte Compare Channel 0 Interrupt Flag

The Low byte Compare Interrupt (LCMPn) flag is set on a compare match on the corresponding compare channel in the low byte timer.

For all modes of operation, the LCMPn flag will be set when a compare match occurs between the Low Byte Timer Counter (TCAn.LCNT) register and the corresponding Compare n (TCAn.LCMPn) register. The LCMPn flag will not be cleared automatically and has to be cleared by software. This is done by writing a ‘1’ to its bit location.

Bit 1 – HUNF: High byte Underflow Interrupt Flag

High byte Underflow Interrupt Flag

This flag is set on a high byte timer BOTTOM (underflow) condition. HUNF is not automatically cleared and needs to be cleared by software. This is done by writing a ‘1’ to its bit location.

Bit 0 – LUNF: Low byte Underflow Interrupt Flag

Low byte Underflow Interrupt Flag

This flag is set on a low byte timer BOTTOM (underflow) condition. LUNF is not automatically cleared and needs to be cleared by software. This is done by writing a ‘1’ to its bit location.