ATtiny1624/1626/1627

CTRLB

Control B - Normal Mode

  0x01 8 - 0x00    

Control B - Normal Mode

Bit  7 6 5 4 3 2 1 0  
    CMP2EN CMP1EN CMP0EN ALUPD WGMODE[2:0]  
Access    R/W R/W R/W R/W R/W R/W R/W  
Reset    0 0 0 0 0 0 0  

Bits 4, 5, 6 – CMPEN: Compare n Enable

Compare n Enable

In the FRQ and PWM Waveform Generation modes, the Compare n Enable (CMPnEN) bits will make the waveform output available on the pin corresponding to WOn, overriding the value in the corresponding PORT output register. The corresponding pin direction must be configured as an output in the PORT peripheral.
ValueDescription
0 Waveform output WOn will not be available on the corresponding pin
1 Waveform output WOn will override the output value of the corresponding pin

Bit 3 – ALUPD: Auto-Lock Update

Auto-Lock Update

The Auto-Lock Update bit controls the Lock Update (LUPD) bit in the TCAn.CTRLE register. When ALUPD is written to ‘1’, the LUPD bit will be set to ‘1’ until the Buffer Valid (CMPnBV) bits of all enabled compare channels are ‘1’. This condition will clear the LUPD bit.

It will remain cleared until the next UPDATE condition, where the buffer values will be transferred to the CMPn registers, and the LUPD bit will be set to ‘1’ again. This makes sure that the CMPnBUF register values are not transferred to the CMPn registers until all enabled compare buffers are written.

ValueDescription
0 LUPD bit in the TCAn.CTRLE register is not altered by the system
1 LUPD bit in the TCAn.CTRLE register is set and cleared automatically

Bits 2:0 – WGMODE[2:0]: Waveform Generation Mode

Waveform Generation Mode

This bit field selects the Waveform Generation mode and controls the counting sequence of the counter, TOP value, UPDATE condition, Interrupt condition, and the type of waveform generated.

No waveform generation is performed in the Normal mode of operation. For all other modes, the waveform generator output will only be directed to the port pins if the corresponding CMPnEN bit has been set. The port pin direction must be set as output.

Table 1. Timer Waveform Generation Mode
Value Group Configuration Mode of Operation TOP UPDATE OVF
0x0 NORMAL Normal PER TOP(1) TOP(1)
0x1 FRQ Frequency CMP0 TOP(1) TOP(1)
0x2 - Reserved - - -
0x3 SINGLESLOPE Single-slope PWM PER BOTTOM BOTTOM
0x4 - Reserved - - -
0x5 DSTOP Dual-slope PWM PER BOTTOM TOP
0x6 DSBOTH Dual-slope PWM PER BOTTOM TOP and BOTTOM
0x7 DSBOTTOM Dual-slope PWM PER BOTTOM BOTTOM
Note:
  1. 1.When counting up.