ATtiny1624/1626/1627

Main Clock Control A

Name:
MCLKCTRLA
Offset:
0x00
Reset:
0x00
Access:
Configuration Change Protection
Bit76543210
CLKOUTCLKSEL[1:0]
AccessR/WR/WR/W
Reset000

Bit 7 – CLKOUT: System Clock Out

System Clock Out

When this bit is written to ‘1’, the system clock is output to the CLKOUT pin.

When the device is in a Sleep mode, there is no clock output unless a peripheral is using the system clock.

Bits 1:0 – CLKSEL[1:0]: Clock Select

Clock Select

This bit field selects the source for the Main Clock (CLK_MAIN).

ValueNameDescription
0x0 OSC20M 20 MHz internal oscillator
0x1 OSCULP32K 32.768 kHz internal ultra low-power oscillator
0x2 XOSC32K 32.768 kHz external crystal oscillator
0x3 EXTCLK External clock