CTRLA

ATtiny1624/1626/1627

Control A

Name:: CTRLA
Offset:: 0x00
Reset:: 0x00
Access:: -

Bit7	6	5	4	3	2	1	0
	RUNSTDBY	CASCADE	SYNCUPD	CLKSEL[2:0]			ENABLE
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0

Bit 6 – RUNSTDBY: Run Standby

Run Standby

Writing a ‘1’ to this bit will enable the peripheral to run in Standby sleep mode.

Bit 5 – CASCADE: Cascade Two Timer/Counters

Cascade Two Timer/Counters

Writing this bit to ‘1’ enables cascading of two 16-bit Timer/Counters type B (TCBn) for 32-bit operation using the Event System. This bit must be ‘1’ for the timer/counter used for the two Most Significant Bytes (MSB). When this bit is ‘1’, the selected event source for capture (CAPT) is delayed by one peripheral clock cycle. This compensates the carry propagation delay when cascading two counters via the Event System.

Bit 4 – SYNCUPD: Synchronize Update

Synchronize Update

When this bit is written to ‘1’, the TCB will restart whenever TCAn is restarted or overflows. This can be used to synchronize capture with the PWM period. If TCAn is selected as the clock source, the TCB will restart when that TCAn is restarted. For other clock selections, it will restart together with TCA0.

Bits 3:1 – CLKSEL[2:0]: Clock Select

Clock Select

Writing these bits selects the clock source for this peripheral.

Value	Name	Description
`0x0`	DIV1	CLK_PER
`0x1`	DIV2	CLK_PER / 2
`0x2`	TCA0	Use CLK_TCA from TCA0
`0x3-0x6`	-	Reserved
`0x7`	EVENT	Positive edge on event input

Bit 0 – ENABLE: Enable

Enable

Writing this bit to ‘1’ enables the Timer/Counter type B peripheral.