ATtiny1624/1626/1627

MBAUD

Host Baud Rate

  0x06 8 - 0x00    

Host Baud Rate

Bit  7 6 5 4 3 2 1 0  
  BAUD[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 7:0 – BAUD[7:0]: Baud Rate

Baud Rate

This bit field is used to derive the SCL high and low time. It must be written while the host is disabled. The host can be disabled by writing ‘0’ to the Enable TWI Host (ENABLE) bit from the Host Control A (TWIn.MCTRLA) register.

Refer to the Clock Generation section for more information on how to calculate the frequency of the SCL.