System Configuration 0

The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the Reset value.

  0x05 8 - 0xF6    

System Configuration 0

Bit  7 6 5 4 3 2 1 0  
Access  R R   R R R   R  
Reset  1 1   1 0 1   0  

Bits 7:6 – CRCSRC[1:0]: CRC Source

CRC Source

See the CRC description for more information about the functionality.
0x0 FLASH CRC of full Flash (boot, application code and application data)
0x1 BOOT CRC of the boot section
0x2 BOOTAPP CRC of application code and boot sections

Bit 4 – TOUTDIS: Time-Out Disable

Time-Out Disable

This bit can disable the blocking of NVM writes after POR.

When the TOUTDIS bit in FUSE.SYSCFG0 is ‘0’ and the RSTPINCFG bit field in FUSE.SYSCFG0 is configured to GPIO or RESET, there will be a time-out period after POR that blocks NVM writes.

The NVM write block will last for 768 OSC32K cycles after POR. The EEBUSY and FBUSY bits in the NVMCTRL.STATUS register must read ‘0’ before the page buffer can be filled or NVM commands can be issued.

0 NVM write block is enabled
1 NVM write block is disabled

Bits 3:2 – RSTPINCFG[1:0]: Reset Pin Configuration

Reset Pin Configuration

This bit selects the pin configuration for the Reset pin.
Note: When configuring the Reset pin as GPIO, there is a potential conflict between the GPIO actively driving the output, and a high-voltage UPDI enable sequence initiation. To avoid this, the GPIO output driver is disabled for 768 OSC32K cycles after a System Reset. Enable any interrupts for this pin only after this period.
0x0 GPIO
0x1 UPDI
0x3 UPDI w/alternate RESET pin

Bit 0 – EESAVE: EEPROM Save Across Chip Erase

EEPROM Save Across Chip Erase

This bit controls if the EEPROM is being erased during a Chip Erase. If enabled, only the Flash memory will be erased by the Chip Erase. If the device is locked, the EEPROM is always erased by a Chip Erase regardless of this bit.
0 EEPROM erased during Chip Erase
1 EEPROM not erased under Chip Erase