ATtiny1624/1626/1627

Conversion Timing

Some of the analog modules in the ADC are disabled between conversions and require time to initialize before a conversion starts. Only the modules used by the current ADC configuration are enabled, and as the initializations run in parallel, the limiting factor is the module with the slowest initialization time. The following table shows the different initialization times needed by the analog modules.

Table 1. ADC Initialization Timing
Analog Module Initialization Time
ADC 10 µs(1)
PGA 20 µs
Settling of internal references 60 µs
Internal Tempsense input 35 µs
Internal DAC input 35 µs
Note:
  1. 1.If CLK_PER < 2 MHz, the ADC initialization time is 20 CLK_PER cycles.

Example: Selecting Tempsense as input and using VDD as the reference will give a 35 µs initialization time. Using the Tempsense with the 1.024V internal reference will result in a 60 µs initialization time.

The ADC can be put in Low-Latency mode by writing a ‘1’ to the LOWLAT bit in the Control A (ADCn.CTRLA) register. This will keep the configured modules continuously enabled, effectively removing all initialization time at the start of a conversion. The initialization time is still needed when enabling the ADC for the first time, and if reconfiguring the ADC to use an input or reference that requires initialization, as shown in the table above. The ADC Busy (ADCBUSY) bit in the Status (ADCn.STATUS) register can be used to check if initialization is ongoing.

The sampling period of the input to the ADC is configured through the Sample Duration (SAMPDUR) bit field in the Control E (ADCn.CTRLE) register as (SAMPDUR + ½) CLK_ADC cycles. The input signal characteristics affect how long the sampling period has to be.

When the PGA is used, it is sampling continuously and will only be in the Hold state when the ADC is sampling the PGA. This ADC PGA Sample Duration (ADCPGASAMPDUR) depends on fCLK_ADC and is configured in the PGA Control (ADCn.PGACTRL) register. SAMPDUR will still configure the minimum sampling period of the input to the PGA as (SAMPDUR + 1) CLK_ADC cycles. In Burst mode, SAMPDUR must be ≥12, limited by the length of the Conversion state.

The Series and Burst Accumulation modes can be used for oversampling to achieve up to 5 bit higher resolution, given suitable input signal and sampling frequency. Increasing the resolution by n bits can be achieved by accumulating 4n samples and dividing the accumulated result by 2n. The Sample Accumulation Number (SAMPNUM) bit field in the Control F (ADCn.CTRLF) register can be configured for up to 45 = 1024 samples, resulting in up to 17-bit resolution.

The two tables below show the calculated conversion rates (fconv) for a subset of the possible combinations of fCLK_ADC and sample durations. For more details, see the relevant timing diagrams on the following pages.

Table 2. Example Conversion Rates (fconv) for fCLK_ADC = 5 MHz and ADCPGASAMPDUR = 20
SAMPDUR PGA fconv(1) Single 8-bit [sps] fconv(1) Single 12-bit [sps] fconv Burst Accumulation [sps]
2 OFF 384615 294118 312500
12 OFF 217391 185185 192308
48 OFF 84746 79365 80645
255 OFF 18797 18519 18587
2 ON 149254 133333 N/A
12 ON 114943 105263 147059
48 ON 62893 59880 71429
255 ON 17452 17212 18051
Table 3. Example Conversion Rates (fconv) for fCLK_ADC = 333 kHz and ADCPGASAMPDUR = 6
SAMPDUR PGA fconv(1) Single 8-bit [sps] fconv(1) Single 12-bit [sps] fconv Burst Accumulation [sps]
2 OFF 25641 19608 20833
12 OFF 14493 12346 12821
48 OFF 5650 5291 5376
255 OFF 1253 1235 1239
2 ON 17094 14184 N/A
12 ON 11299 9950 16667
48 ON 5089 4796 5952
255 ON 1223 1206 1267
Note:
  1. 1.Conversion rates with the Free-Running (FREERUN) bit set to ‘1’ in the Control F (ADCn.CTRLF) register; a new conversion will be started immediately after the results are available in the ADC.
Parent topic: Operation