ATtiny1624/1626/1627

SP

Stack Pointer

The CPU.SP register holds the Stack Pointer (SP) that points to the top of the stack. After being reset, the SP points to the highest internal SRAM address.

Only the number of bits required to address the available data memory, including external memory (up to 64 KB), is implemented for each device. Unused bits will always read ‘0’.

The CPU.SPL and CPU.SPH register pair represents the 16-bit value, CPU.SP. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.

To prevent corruption when updating the SP from software, a write to CPU.SPL will automatically disable interrupts for the next four instructions or until the next I/O memory write, whichever comes first.

  0x0D 16 - Top of stack    

Stack Pointer

Bit  15 14 13 12 11 10 9 8  
  SP[15:8]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset                   
Bit  7 6 5 4 3 2 1 0  
  SP[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset                   

Bits 15:8 – SP[15:8]: Stack Pointer High Byte

Stack Pointer High Byte

These bits hold the MSB of the 16-bit register.

Bits 7:0 – SP[7:0]: Stack Pointer Low Byte

Stack Pointer Low Byte

These bits hold the LSB of the 16-bit register.