ATtiny1624/1626/1627

PER

Period

The RTC.PERL and RTC.PERH register pair represents the 16-bit value, RTC.PER. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.

Due to the synchronization between the RTC clock and main clock domains, there is a latency of two RTC clock cycles from updating the register until this has an effect. The application software needs to check that the PERBUSY flag in RTC.STATUS is cleared before writing to this register.

  0x0A 16 - 0xFFFF    

Period

Bit  15 14 13 12 11 10 9 8  
  PER[15:8]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  1 1 1 1 1 1 1 1  
Bit  7 6 5 4 3 2 1 0  
  PER[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  1 1 1 1 1 1 1 1  

Bits 15:8 – PER[15:8]: Period High Byte

Period High Byte

These bits hold the MSB of the 16-bit Period register.

Bits 7:0 – PER[7:0]: Period Low Byte

Period Low Byte

These bits hold the LSB of the 16-bit Period register.