ATtiny1624/1626/1627

CTRLA

Control A

  0x00 8 - 0x00    

Control A

Bit  7 6 5 4 3 2 1 0  
        SDASETUP SDAHOLD[1:0] FMPEN    
Access        R/W R/W R/W R/W    
Reset        0 0 0 0    

Bit 4 – SDASETUP: SDA Setup Time

SDA Setup Time

This bit controls the number of cycles the SCL is stretched to ensure sufficient setup time on the SDA out signal. This bit is used when operating in client mode.

ValueNameDescription
0 4CYC SDA setup time is four clock cycles
1 8CYC SDA setup time is eight clock cycles

Bits 3:2 – SDAHOLD[1:0]: SDA Hold Time

SDA Hold Time

Writing this bit field selects the SDA hold time for the TWI. See the Electrical Characteristics section for details.

ValueNameDescription
0x0 OFF Hold time OFF
0x1 50NS Short hold time
0x2 300NS Meets the SMBus 2.0 specifications under typical conditions
0x3 500NS Meets the SMBus 2.0 specifications across all corners

Bit 1 – FMPEN: FM Plus Enable

FM Plus Enable

Writing a ‘1’ to this bit selects the 1 MHz bus speed (Fast mode plus, Fm+) for the TWI in default configuration.

ValueDescription
0 Operating in Standard mode or Fast mode
1 Operating in Fast mode plus