ATtiny1624/1626/1627

CTRLA

Control A

  0x00 8 - 0x00  

Control A

Bit  7 6 5 4 3 2 1 0  
    DORD MASTER CLK2X   PRESC[1:0] ENABLE  
Access    R/W R/W R/W   R/W R/W R/W  
Reset    0 0 0   0 0 0  

Bit 6 – DORD: Data Order

Data Order

ValueDescription
0 The MSb of the data word is transmitted first
1 The LSb of the data word is transmitted first

Bit 5 – MASTER: Host/Client Select

Host/Client Select

This bit selects the desired SPI mode.

If SS is configured as input and driven low while this bit is ‘1’, then this bit is cleared, and the IF in SPIn.INTFLAGS is set. The user has to write MASTER = 1 again to re-enable SPI Host mode.

This behavior is controlled by the Client Select Disable (SSD) bit in SPIn.CTRLB.

ValueDescription
0 SPI Client mode selected
1 SPI Host mode selected

Bit 4 – CLK2X: Clock Double

Clock Double

When this bit is written to ‘1’, the SPI speed (SCK frequency, after internal prescaler) is doubled in Host mode.

ValueDescription
0 SPI speed (SCK frequency) is not doubled
1 SPI speed (SCK frequency) is doubled in Host mode

Bits 2:1 – PRESC[1:0]: Prescaler

Prescaler

This bit field controls the SPI clock rate configured in Host mode. These bits have no effect in Client mode. The relationship between SCK and the peripheral clock frequency (fCLK_PER) is shown below.

The output of the SPI prescaler can be doubled by writing the CLK2X bit to ‘1’.
ValueNameDescription
0x0 DIV4 CLK_PER/4
0x1 DIV16 CLK_PER/16
0x2 DIV64 CLK_PER/64
0x3 DIV128 CLK_PER/128

Bit 0 – ENABLE: SPI Enable

SPI Enable

ValueDescription
0 SPI is disabled
1 SPI is enabled