The figure below shows the timing diagram for the ADC when running in Single 8- or 12-bit mode without using the PGA.
Figure 1. Timing Diagram - Single
Conversion
Notes:
- 1.In Single 8-bit mode, the length of the Conversion state is nine CLK_ADC cycles. In all other modes, it is thirteen cycles.
- 2.If the Low Latency (LOWLAT) bit is set to ‘
1’ in the Control A (ADCn.CTRLA) register, the analog modules in the ADC will not turn OFF at the end of the conversion, eliminating the initialization time when triggering the following conversion. - 3.The time from the conversion has finished to the outputs are available in the registers is 0.5 CLK_ADC cycles followed by 1 CLK_MAIN cycle. With minimum prescaling, this sums up to 1 CLK_ADC cycle.
The total conversion time (tconv) for a single result, in μs, is calculated by:
A new conversion starts immediately after a result is
available in the Result (ADCn.RESULT) register if the Free-Running (FREERUN) bit is set to
‘1’ in the Control F (ADCn.CTRLF) register. The Free-Running conversion
rate (fconv) is calculated by: