ATtiny1624/1626/1627

CTRLA

Control A

  0x05 8 - 0x00    

Control A

Bit  7 6 5 4 3 2 1 0  
  RXCIE TXCIE DREIE RXSIE LBME ABEIE   RS485  
Access  R/W R/W R/W R/W R/W R/W   R/W  
Reset  0 0 0 0 0 0   0  

Bit 0 – RS485: RS-485 Mode

RS-485 Mode

This bit controls whether the RS-485 mode is enabled or not. Refer to section RS-485 Mode for more information.
ValueDescription
0 RS-485 mode is disabled
1 RS-485 mode is enabled

Bit 2 – ABEIE: Auto-Baud Error Interrupt Enable

Auto-Baud Error Interrupt Enable

This bit controls whether the Auto-baud Error Interrupt is enabled or not. When enabled, the interrupt will be triggered when the ISFIF bit in the USARTn.STATUS register is set.
ValueDescription
0 The Auto-Baud Error Interrupt is disabled
1 The Auto-Baud Error Interrupt is enabled

Bit 3 – LBME: Loop-Back Mode Enable

Loop-Back Mode Enable

This bit controls whether the Loop-back mode is enabled or not. When enabled, an internal connection between the TXD pin and the USART receiver is created, and the input from the RXD pin to the USART receiver is disconnected.
ValueDescription
0 Loop-back mode is disabled
1 Loop-back mode is enabled

Bit 4 – RXSIE: Receiver Start Frame Interrupt Enable

Receiver Start Frame Interrupt Enable

This bit controls whether the Receiver Start Frame Interrupt is enabled or not. When enabled, the interrupt will be triggered when the RXSIF bit in the USARTn.STATUS register is set.
ValueDescription
0 The Receiver Start Frame Interrupt is disabled
1 The Receiver Start Frame Interrupt is enabled

Bit 5 – DREIE: Data Register Empty Interrupt Enable

Data Register Empty Interrupt Enable

This bit controls whether the Data Register Empty Interrupt is enabled or not. When enabled, the interrupt will be triggered when the DREIF bit in the USARTn.STATUS register is set.
ValueDescription
0 The Data Register Empty Interrupt is disabled
1 The Data Register Empty Interrupt is enabled

Bit 6 – TXCIE: Transmit Complete Interrupt Enable

Transmit Complete Interrupt Enable

This bit controls whether the Transmit Complete Interrupt is enabled or not. When enabled, the interrupt will be triggered when the TXCIF bit in the USARTn.STATUS register is set.
ValueDescription
0 The Transmit Complete Interrupt is disabled
1 The Transmit Complete Interrupt is enabled

Bit 7 – RXCIE: Receive Complete Interrupt Enable

Receive Complete Interrupt Enable

This bit controls whether the Receive Complete Interrupt is enabled or not. When enabled, the interrupt will be triggered when the RXCIF bit in the USARTn.STATUS register is set.
ValueDescription
0 The Receive Complete Interrupt is disabled
1 The Receive Complete Interrupt is enabled