ATtiny1624/1626/1627

DIR

Data Direction

Access to the Virtual PORT registers has the same outcome as access to the regular registers but allows for memory specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space where the regular PORT registers reside.

  0x00 8 - 0x00    

Data Direction

Bit  7 6 5 4 3 2 1 0  
  DIR[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 7:0 – DIR[7:0]: Data Direction

Data Direction

This bit field controls the output driver for each PORTx pin.

This bit field does not control the digital input buffer. The digital input buffer for pin n (Pxn) can be configured in the Input/Sense Configuration (ISC) bit field in the Pin n Control (PORTx.PINnCTRL) register.

The available configuration for each bit n in this bit field is shown in the table below.

ValueDescription
0 Pxn is configured as an input-only pin, and the output driver is disabled
1 Pxn is configured as an output pin, and the output driver is enabled