ATtiny1624/1626/1627

CTRLA

Control A

If an NMI has been triggered this register is not writable.

  0x00 8 - 0x00    

Control A

Bit  7 6 5 4 3 2 1 0  
  RESET           NMIEN ENABLE  
Access  R/W           R/W R/W  
Reset  0           0 0  

Bit 7 – RESET: Reset CRCSCAN

Reset CRCSCAN

Writing this bit to ‘1’ resets the CRCSCAN peripheral. The CRCSCAN Control registers and Status register (CRCSCAN.CTRLA, CRCSCAN.CTRLB, CRCSCAN.STATUS) will be cleared one clock cycle after the RESET bit is written to ‘1’.

If NMIEN is ‘0’, this bit is writable both when the CRCSCAN is busy (the BUSY bit in CRCSCAN.STATUS is ‘1’) and not busy (the BUSY bit is ‘0’), and will take effect immediately.

If NMIEN is ‘1’, this bit is only writable when the CRCSCAN is not busy (the BUSY bit in CRCSCAN.STATUS is ‘0’).

The RESET bit is a strobe bit.

Bit 1 – NMIEN: Enable NMI Trigger

Enable NMI Trigger

When this bit is written to ‘1’, any CRC failure will trigger an NMI.

This bit can only be cleared by a system Reset - it is not cleared by a write to the RESET bit.

This bit can only be written to ‘1’ when the CRCSCAN is not busy (the BUSY bit in CRCSCAN.STATUS is ‘0’).

Bit 0 – ENABLE: Enable CRCSCAN

Enable CRCSCAN

Writing this bit to ‘1’ enables the CRCSCAN peripheral with the current settings. It will stay ‘1’ even after a CRC check has completed, but writing it to ‘1’ again will start a new check.

Writing the bit to ‘0’ has no effect

The CRCSCAN can be configured to run a scan during the MCU start-up sequence to verify the Flash sections before letting the CPU start normal code execution (see the Initialization section). If this feature is enabled, the ENABLE bit will read as ‘1’ when normal code execution starts.

To see whether the CRCSCAN peripheral is busy with an ongoing check, poll the BUSY bit in the Status register (CRCSCAN.STATUS).