ATtiny1624/1626/1627

CTRLE

Control E

  0x08 8 - 0x00    

Control E

Bit  7 6 5 4 3 2 1 0  
  SAMPDUR[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 7:0 – SAMPDUR[7:0]: Sample Duration

Sample Duration

This bit field controls the input sample duration in ADC clock (CLK_ADC) cycles. The sample duration without the PGA is (SAMPDUR + ½) CLK_ADC cycles.

If the PGA is used, the input sample duration is (SAMPDUR + 1) CLK_ADC cycles, while the ADC PGA Sample Duration (ADCPGASAMPDUR) bit field in the PGA Control (ADCn.PGACTRL) register controls how long the ADC will sample the PGA.