Control E
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SAMPDUR[7:0] | |||||||
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Sample Duration
This bit field controls the input sample duration in ADC clock (CLK_ADC) cycles. The sample duration without the PGA is (SAMPDUR + ½) CLK_ADC cycles.
If the PGA is used, the input sample duration is (SAMPDUR + 1) CLK_ADC cycles, while the ADC PGA Sample Duration (ADCPGASAMPDUR) bit field in the PGA Control (ADCn.PGACTRL) register controls how long the ADC will sample the PGA.