ATtiny1624/1626/1627

OUT

Output Value

Access to the Virtual PORT registers has the same outcome as access to the regular registers but allows for memory specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space where the regular PORT registers reside.

  0x01 8 - 0x00    

Output Value

Bit  7 6 5 4 3 2 1 0  
  OUT[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 7:0 – OUT[7:0]: Output Value

Output Value

This bit field controls the output driver level for each PORTx pin.

This configuration only has an effect when the output driver (PORTx.DIR) is enabled for the corresponding pin.

The available configuration for each bit n in this bit field is shown in the table below.

ValueDescription
0 The pin n (Pxn) output is driven low
1 The Pxn output is driven high